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Searched refs:FMC_BTR3_ADDSET_Pos (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f302xe.h8178 #define FMC_BTR3_ADDSET_Pos (0U) macro
8179 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8181 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8182 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8183 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8184 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f303xe.h8741 #define FMC_BTR3_ADDSET_Pos (0U) macro
8742 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8744 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8745 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8746 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8747 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f398xx.h8679 #define FMC_BTR3_ADDSET_Pos (0U) macro
8680 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8682 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8683 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8684 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8685 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h6881 #define FMC_BTR3_ADDSET_Pos (0U) macro
6882 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
6884 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
6885 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
6886 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
6887 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f722xx.h6865 #define FMC_BTR3_ADDSET_Pos (0U) macro
6866 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
6868 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
6869 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
6870 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
6871 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f730xx.h7095 #define FMC_BTR3_ADDSET_Pos (0U) macro
7096 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7098 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7099 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7100 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7101 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f733xx.h7095 #define FMC_BTR3_ADDSET_Pos (0U) macro
7096 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7098 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7099 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7100 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7101 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f732xx.h7079 #define FMC_BTR3_ADDSET_Pos (0U) macro
7080 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7082 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7083 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7084 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7085 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f750xx.h7899 #define FMC_BTR3_ADDSET_Pos (0U) macro
7900 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7902 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7903 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7904 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7905 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f745xx.h7656 #define FMC_BTR3_ADDSET_Pos (0U) macro
7657 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7659 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7660 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7661 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7662 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f756xx.h7899 #define FMC_BTR3_ADDSET_Pos (0U) macro
7900 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7902 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7903 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7904 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7905 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f746xx.h7711 #define FMC_BTR3_ADDSET_Pos (0U) macro
7712 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7714 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7715 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7716 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7717 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f765xx.h8169 #define FMC_BTR3_ADDSET_Pos (0U) macro
8170 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8172 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8173 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8174 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8175 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f777xx.h8451 #define FMC_BTR3_ADDSET_Pos (0U) macro
8452 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8454 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8455 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8456 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8457 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f767xx.h8263 #define FMC_BTR3_ADDSET_Pos (0U) macro
8264 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8266 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8267 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8268 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8269 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f779xx.h8534 #define FMC_BTR3_ADDSET_Pos (0U) macro
8535 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8537 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8538 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8539 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8540 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f769xx.h8346 #define FMC_BTR3_ADDSET_Pos (0U) macro
8347 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8349 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8350 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8351 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8352 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h7594 #define FMC_BTR3_ADDSET_Pos (0U) macro
7595 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7597 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7598 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7599 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7600 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f446xx.h7363 #define FMC_BTR3_ADDSET_Pos (0U) macro
7364 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7366 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7367 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7368 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7369 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f429xx.h7653 #define FMC_BTR3_ADDSET_Pos (0U) macro
7654 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7656 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7657 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7658 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7659 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f439xx.h7840 #define FMC_BTR3_ADDSET_Pos (0U) macro
7841 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7843 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7844 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7845 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7846 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f437xx.h7786 #define FMC_BTR3_ADDSET_Pos (0U) macro
7787 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7789 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7790 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7791 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7792 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f469xx.h10803 #define FMC_BTR3_ADDSET_Pos (0U) macro
10804 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
10806 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
10807 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
10808 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
10809 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f479xx.h10993 #define FMC_BTR3_ADDSET_Pos (0U) macro
10994 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
10996 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
10997 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
10998 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
10999 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h18337 #define FMC_BTR3_ADDSET_Pos (0U) macro
18338 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
18340 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
18341 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
18342 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
18343 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */

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