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Searched refs:FMC_BTR1_ADDSET_Pos (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f302xe.h8060 #define FMC_BTR1_ADDSET_Pos (0U) macro
8061 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8063 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8064 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8065 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8066 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f303xe.h8623 #define FMC_BTR1_ADDSET_Pos (0U) macro
8624 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8626 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8627 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8628 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8629 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f398xx.h8561 #define FMC_BTR1_ADDSET_Pos (0U) macro
8562 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8564 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8565 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8566 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8567 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h6775 #define FMC_BTR1_ADDSET_Pos (0U) macro
6776 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6778 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6779 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6780 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6781 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f722xx.h6759 #define FMC_BTR1_ADDSET_Pos (0U) macro
6760 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6762 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6763 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6764 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6765 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f730xx.h6989 #define FMC_BTR1_ADDSET_Pos (0U) macro
6990 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6992 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6993 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6994 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6995 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f733xx.h6989 #define FMC_BTR1_ADDSET_Pos (0U) macro
6990 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6992 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6993 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6994 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6995 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f732xx.h6973 #define FMC_BTR1_ADDSET_Pos (0U) macro
6974 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6976 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6977 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6978 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6979 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f750xx.h7793 #define FMC_BTR1_ADDSET_Pos (0U) macro
7794 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7796 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7797 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7798 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7799 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f745xx.h7550 #define FMC_BTR1_ADDSET_Pos (0U) macro
7551 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7553 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7554 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7555 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7556 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f756xx.h7793 #define FMC_BTR1_ADDSET_Pos (0U) macro
7794 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7796 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7797 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7798 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7799 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f746xx.h7605 #define FMC_BTR1_ADDSET_Pos (0U) macro
7606 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7608 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7609 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7610 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7611 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f765xx.h8063 #define FMC_BTR1_ADDSET_Pos (0U) macro
8064 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8066 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8067 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8068 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8069 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f777xx.h8345 #define FMC_BTR1_ADDSET_Pos (0U) macro
8346 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8348 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8349 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8350 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8351 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f767xx.h8157 #define FMC_BTR1_ADDSET_Pos (0U) macro
8158 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8160 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8161 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8162 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8163 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f779xx.h8428 #define FMC_BTR1_ADDSET_Pos (0U) macro
8429 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8431 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8432 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8433 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8434 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f769xx.h8240 #define FMC_BTR1_ADDSET_Pos (0U) macro
8241 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8243 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8244 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8245 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8246 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h7476 #define FMC_BTR1_ADDSET_Pos (0U) macro
7477 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7479 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7480 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7481 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7482 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f446xx.h7245 #define FMC_BTR1_ADDSET_Pos (0U) macro
7246 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7248 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7249 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7250 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7251 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f429xx.h7535 #define FMC_BTR1_ADDSET_Pos (0U) macro
7536 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7538 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7539 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7540 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7541 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f439xx.h7722 #define FMC_BTR1_ADDSET_Pos (0U) macro
7723 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7725 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7726 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7727 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7728 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f437xx.h7668 #define FMC_BTR1_ADDSET_Pos (0U) macro
7669 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7671 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7672 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7673 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7674 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f469xx.h10685 #define FMC_BTR1_ADDSET_Pos (0U) macro
10686 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
10688 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
10689 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
10690 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
10691 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f479xx.h10875 #define FMC_BTR1_ADDSET_Pos (0U) macro
10876 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
10878 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
10879 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
10880 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
10881 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h18207 #define FMC_BTR1_ADDSET_Pos (0U) macro
18208 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
18210 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
18211 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
18212 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
18213 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */

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