1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_FLASH_EX_H 21 #define STM32H5xx_HAL_FLASH_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASHEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Mass erase or sector Erase. 49 This parameter can be a value of @ref FLASH_Type_Erase */ 50 51 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 52 This parameter can be a value of @ref FLASH_Banks 53 (FLASH_BANK_BOTH should be used only for mass erase) */ 54 55 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 56 This parameter can be a value of @ref FLASH_Sectors */ 57 58 uint32_t NbSectors; /*!< Number of sectors to be erased. 59 This parameter can be a value between 1 and (max number of sectors in the bank - 60 value of initial sector)*/ 61 } FLASH_EraseInitTypeDef; 62 63 64 /** 65 * @brief FLASH Option Bytes Program structure definition 66 */ 67 typedef struct 68 { 69 uint32_t OptionType; /*!< Option byte to be configured. 70 This parameter can be a value of @ref FLASH_Option_Type */ 71 72 uint32_t ProductState; /*!< Set the product state. 73 This parameter can be a value of @ref FLASH_OB_Product_State */ 74 75 uint32_t USERType; /*!< Select the User Option Byte(s) to be configured (used for OPTIONBYTE_USER). 76 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 77 78 uint32_t USERConfig; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 80 @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP, 82 @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV, 83 @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, 84 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE, 85 @ref FLASH_OB_USER_SWAP_BANK */ 86 87 uint32_t USERConfig2; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 88 This parameter can be a combination of @ref FLASH_OB_USER_SRAM1_3_RST, 89 @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC, 90 @ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC, 91 @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC, 92 @ref FLASH_OB_USER_USBPD_DIS, @ref FLASH_OB_USER_TZEN */ 93 94 uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration. 95 This parameter must be a value of @ref FLASH_Banks */ 96 97 uint32_t WRPState; /*!< Write protection activation or deactivation. 98 This parameter can be a value of @ref FLASH_WRP_State */ 99 100 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 101 The value of this parameter depend on device used within the same series */ 102 103 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured: secure or non-secure. 104 This parameter must be a value of @ref FLASH_OB_BOOT_CONFIG enumeration */ 105 106 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 107 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 108 109 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 110 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 111 112 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. 113 This parameter must be a value of @ref FLASH_OTP_Blocks */ 114 115 uint32_t HDPStartSector; /*!< Start sector of HDP area (used for OPTIONBYTE_HDP). 116 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 117 118 uint32_t HDPEndSector; /*!< End sector of HDP area (used for OPTIONBYTE_HDP). 119 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 120 121 uint32_t EDATASize; /*!< Specifies the number of Flash high-cycle sectors. 122 This parameter must be a value between 0 and 8 (sectors) */ 123 124 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 125 uint32_t WMSecStartSector; /*!< Start sector of secure area (used for OPTIONBYTE_WMSEC). 126 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 127 uint32_t WMSecEndSector; /*!< End sector of secure area (used for OPTIONBYTE_WMSEC). 128 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 129 #endif /* __ARM_FEATURE_CMSE */ 130 131 } FLASH_OBProgramInitTypeDef; 132 133 /** 134 * @brief FLASHEx Block-based attributes structure definition 135 */ 136 typedef struct 137 { 138 uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. 139 This parameter must be a value of @ref FLASH_Banks */ 140 uint32_t BBAttributesType; /*!< Block-Based Attributes type. 141 This parameter must be a value of @ref FLASH_BB_Attributes 142 */ 143 uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration 144 of a sector: 145 0 means sector non-protected, 1 means sector protected. 146 Protection (secure or privilege) depends on 147 BBAttributesType value */ 148 } FLASH_BBAttributesTypeDef; 149 150 /** 151 * @brief FLASHEx Operation structure definition 152 */ 153 typedef struct 154 { 155 uint32_t OperationType; /*!< Flash operation Type. 156 This parameter must be a value of @ref FLASH_Operation_Type */ 157 uint32_t FlashArea; /*!< Flash operation memory area. 158 This parameter must be a value of @ref FLASH_Operation_Area */ 159 uint32_t Address; /*!< Flash operation Address offset. 160 This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ 161 } FLASH_OperationTypeDef; 162 163 /** 164 * @brief FLASH HDP Extension structure definition 165 */ 166 typedef struct 167 { 168 uint32_t Banks; /*!< Selection of the associated bank of HDP Area. 169 This parameter must be a value of @ref FLASH_Banks */ 170 uint32_t NbSectors; /*!< Number of sectors to be HDP extended. 171 This parameter can be a value between 1 and max number of sectors in the bank */ 172 } FLASH_HDPExtensionTypeDef; 173 174 /** 175 * @brief ECC Info Structure definition 176 */ 177 typedef struct 178 { 179 uint32_t Area; /*!< Area from which an ECC was detected. 180 This parameter can be a value of @ref FLASHEx_ECC_Area */ 181 182 uint32_t Address; /*!< ECC error address */ 183 184 uint32_t Data; /*!< ECC failing data */ 185 } FLASH_EccInfoTypeDef; 186 187 /** 188 * @} 189 */ 190 /* Exported constants --------------------------------------------------------*/ 191 192 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants 193 * @{ 194 */ 195 196 /** @defgroup FLASH_Type_Erase FLASH Type Erase 197 * @{ 198 */ 199 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 200 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Secure flash sectors 201 erase activation */ 202 #define FLASH_TYPEERASE_SECTORS_NS (FLASH_CR_SER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash 203 sectors erase activation */ 204 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Secure flash mass erase 205 activation */ 206 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_CR_BER | FLASH_CR_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass 207 erase activation */ 208 #if defined (FLASH_SR_OBKERR) 209 #define FLASH_TYPEERASE_OBK_ALT FLASH_OBKCFGR_ALT_SECT_ERASE /*!< Flash OBK erase 210 activation */ 211 #endif /* FLASH_SR_OBKERR */ 212 #else 213 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Flash sectors erase 214 activation */ 215 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Flash mass erase 216 activation */ 217 #if defined (FLASH_SR_OBKERR) 218 #define FLASH_TYPEERASE_OBK_ALT (FLASH_OBKCFGR_ALT_SECT_ERASE | FLASH_NON_SECURE_MASK) /*!< Flash OBK erase 219 activation */ 220 #endif /* FLASH_SR_OBKERR */ 221 #endif /* __ARM_FEATURE_CMSE */ 222 223 /** @defgroup FLASH_ECC_Area FLASH ECC Area 224 * @brief FLASH ECC Area 225 * @{ 226 */ 227 #define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ 228 #define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCR_BK_ECC /*!< FLASH bank 2 area */ 229 #define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ 230 #if defined (FLASH_SR_OBKERR) 231 #define FLASH_ECC_AREA_OBK FLASH_ECCR_OBK_ECC /*!< FLASH OBK area */ 232 #endif /* FLASH_SR_OBKERR */ 233 #define FLASH_ECC_AREA_OTP FLASH_ECCR_OTP_ECC /*!< FLASH OTP area */ 234 #if defined (FLASH_EDATAR_EDATA_EN) 235 #define FLASH_ECC_AREA_EDATA FLASH_ECCR_DATA_ECC /*!< FLASH high-cycle data area */ 236 #endif /* FLASH_EDATAR_EDATA_EN */ 237 /** 238 * @} 239 */ 240 241 /** 242 * @} 243 */ 244 245 /** @defgroup FLASH_Option_Type FLASH Option Type 246 * @{ 247 */ 248 #define OPTIONBYTE_WRP 0x0001U /*!< WRP option byte configuration */ 249 #define OPTIONBYTE_PROD_STATE 0x0002U /*!< RDP option byte configuration */ 250 #define OPTIONBYTE_USER 0x0004U /*!< USER option byte configuration */ 251 #define OPTIONBYTE_BOOTADDR 0x0008U /*!< BOOT address option byte configuration */ 252 #define OPTIONBYTE_BOOT_LOCK 0x0010U /*!< Boot lock option byte configuration */ 253 #define OPTIONBYTE_OTP_LOCK 0x0020U /*!< OTP Lock option byte configuration */ 254 #define OPTIONBYTE_HDP 0x0040U /*!< Hide Protection area option byte configuration */ 255 #if defined (FLASH_EDATAR_EDATA_EN) 256 #define OPTIONBYTE_EDATA 0x0080U /*!< Flash high-cycle data area option byte configuration */ 257 #endif /* FLASH_EDATAR_EDATA_EN */ 258 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 259 #define OPTIONBYTE_WMSEC 0x0200U /*!< Watermark-based secure area option byte configuration */ 260 #endif /* __ARM_FEATURE_CMSE */ 261 262 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 263 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 264 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 265 OPTIONBYTE_HDP | OPTIONBYTE_EDATA | OPTIONBYTE_WMSEC) /*!< All option 266 byte configuration */ 267 #else 268 #if defined (FLASH_EDATAR_EDATA_EN) 269 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 270 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 271 OPTIONBYTE_HDP | OPTIONBYTE_EDATA) /*!< All option byte configuration */ 272 #else 273 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 274 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 275 OPTIONBYTE_HDP) /*!< All option byte configuration */ 276 #endif /* FLASH_EDATAR_EDATA_EN */ 277 #endif /* __ARM_FEATURE_CMSE */ 278 /** 279 * @} 280 */ 281 282 /** @defgroup FLASH_OB_USER_Type FLASH OB USER Type 283 * @{ 284 */ 285 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 286 #define OB_USER_BORH_EN 0x00000002U /*!< BOR high enable status */ 287 #define OB_USER_IWDG_SW 0x00000004U /*!< Independent watchdog selection */ 288 #define OB_USER_WWDG_SW 0x00000008U /*!< Window watchdog selection */ 289 #define OB_USER_NRST_STOP 0x00000010U /*!< Reset generated when entering the stop mode */ 290 #define OB_USER_NRST_STDBY 0x00000020U /*!< Reset generated when entering the standby mode */ 291 #define OB_USER_IO_VDD_HSLV 0x00000040U /*!< High speed IO at low voltage configuration bit */ 292 #define OB_USER_IO_VDDIO2_HSLV 0x00000080U /*!< High speed IO2 at low voltage configuration bit */ 293 #define OB_USER_IWDG_STOP 0x00000100U /*!< Independent watchdog counter freeze in stop mode */ 294 #define OB_USER_IWDG_STDBY 0x00000200U /*!< Independent watchdog counter freeze in standby mode */ 295 #if defined (FLASH_OPTSR_BOOT_UBE) 296 #define OB_USER_BOOT_UBE 0x00000400U /*!< Unique Boot entry */ 297 #endif /* FLASH_OPTSR_BOOT_UBE */ 298 #define OB_USER_SWAP_BANK 0x00000800U /*!< Swap banks */ 299 300 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 301 #define OB_USER_SRAM1_3_RST 0x00001000U /*!< SRAM1 and SRAM3 erase upon system reset */ 302 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 303 #if defined (FLASH_OPTSR2_SRAM1_RST) 304 #define OB_USER_SRAM1_RST 0x00001000U /*!< SRAM1 Erase when system reset */ 305 #endif /* FLASH_OPTSR2_SRAM1_RST */ 306 #define OB_USER_SRAM2_RST 0x00002000U /*!< SRAM2 Erase when system reset */ 307 #define OB_USER_BKPRAM_ECC 0x00004000U /*!< Backup RAM ECC detection and correction enable */ 308 #define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */ 309 #define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */ 310 #define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */ 311 #if defined (FLASH_OPTSR2_USBPD_DIS) 312 #define OB_USER_USBPD_DIS 0x00040000U /*!< USB power delivery configuration enable */ 313 #endif /*FLASH_OPTSR2_USBPD_DIS*/ 314 #if defined (FLASH_OPTSR2_TZEN) 315 #define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */ 316 #endif /* FLASH_OPTSR2_TZEN */ 317 318 #if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) && defined (FLASH_OPTSR2_USBPD_DIS) 319 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 320 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 321 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 322 OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ 323 OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ 324 OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_USBPD_DIS |\ 325 OB_USER_TZEN) 326 #else 327 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 328 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 329 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 330 OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\ 331 OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\ 332 OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) 333 #endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level 339 * @{ 340 */ 341 #define OB_BOR_LEVEL_1 0U /*!< Reset level 1 threshold */ 342 #define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 2 threshold */ 343 #define OB_BOR_LEVEL_3 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 3 threshold */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup FLASH_OB_USER_BORH_EN FLASH BOR High Enable Status 349 * @{ 350 */ 351 #define OB_BORH_DISABLE 0x00000000U /*!< BOR high status bit disabled */ 352 #define OB_BORH_ENABLE FLASH_OPTSR_BORH_EN /*!< BOR high status bit enabled */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 358 * @{ 359 */ 360 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 361 #define OB_IWDG_SW FLASH_OPTSR_IWDG_SW /*!< Software independent watchdog */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 367 * @{ 368 */ 369 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 370 #define OB_WWDG_SW FLASH_OPTSR_WWDG_SW /*!< Software window watchdog */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes nRST_STOP 376 * @{ 377 */ 378 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering in stop mode */ 379 #define OB_STOP_NORST FLASH_OPTSR_NRST_STOP /*!< No reset generated when entering in stop mode */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes nRST_STDBY 385 * @{ 386 */ 387 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering in standby mode */ 388 #define OB_STANDBY_NORST FLASH_OPTSR_NRST_STDBY /*!< No reset generated when entering in standby mode */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup FLASH_OB_Product_State FLASH Product State 394 * @{ 395 */ 396 #define OB_PROD_STATE_OPEN (0xEDU << FLASH_OPTSR_PRODUCT_STATE_Pos) 397 #define OB_PROD_STATE_PROVISIONING (0x17U << FLASH_OPTSR_PRODUCT_STATE_Pos) 398 #define OB_PROD_STATE_IROT_PROVISIONED (0x2EU << FLASH_OPTSR_PRODUCT_STATE_Pos) 399 #define OB_PROD_STATE_TZ_CLOSED (0xC6U << FLASH_OPTSR_PRODUCT_STATE_Pos) 400 #define OB_PROD_STATE_CLOSED (0x72U << FLASH_OPTSR_PRODUCT_STATE_Pos) 401 #define OB_PROD_STATE_LOCKED (0x5CU << FLASH_OPTSR_PRODUCT_STATE_Pos) 402 #define OB_PROD_STATE_REGRESSION (0x9AU << FLASH_OPTSR_PRODUCT_STATE_Pos) 403 #define OB_PROD_STATE_NS_REGRESSION (0xA3U << FLASH_OPTSR_PRODUCT_STATE_Pos) 404 /** 405 * @} 406 */ 407 408 /** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes VDD IO HSLV 409 * @{ 410 */ 411 #define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled */ 412 #define OB_IO_VDD_HSLV_ENABLE FLASH_OPTSR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled */ 413 /** 414 * @} 415 */ 416 417 /** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes VDDIO2 IO HSLV 418 * @{ 419 */ 420 #define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature 421 disabled */ 422 #define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTSR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature 423 enabled */ 424 /** 425 * @} 426 */ 427 428 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH IWDG Counter Freeze in STOP 429 * @{ 430 */ 431 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< IWDG counter frozen in STOP mode */ 432 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_IWDG_STOP /*!< IWDG counter active in STOP mode */ 433 /** 434 * @} 435 */ 436 437 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH IWDG Counter Freeze in STANDBY 438 * @{ 439 */ 440 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< IWDG counter frozen in STANDBY mode */ 441 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_IWDG_STDBY /*!< IWDG counter active in STANDBY mode */ 442 /** 443 * @} 444 */ 445 446 /** @defgroup FLASH_OB_USER_BOOT_UBE FLASH OB Boot UBE 447 * @{ 448 */ 449 #if defined (FLASH_OPTSR_BOOT_UBE) 450 #define OB_UBE_OEM_IROT (0xB4U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< OEM-iRoT (user flash) selected */ 451 #define OB_UBE_ST_IROT (0xC3U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< ST-iRoT (system flash) selected */ 452 #endif /* FLASH_OPTSR_BOOT_UBE */ 453 /** 454 * @} 455 */ 456 457 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH OB SWAP BANK 458 * @{ 459 */ 460 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 461 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK /*!< Bank swap enabled */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup FLASH_OB_USER_SRAM1_3_RST FLASH Option Bytes SRAM1_3 Erase On Reset 467 * @{ 468 */ 469 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 470 #define OB_SRAM1_3_RST_ERASE 0x00000000U /*!< SRAM1 and SRAM3 erased when a system reset occurs */ 471 #define OB_SRAM1_3_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_RST /*!< SRAM1 and SRAM3 are not erased when a system reset 472 occurs */ 473 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes SRAM1 Erase On Reset 479 * @{ 480 */ 481 #if defined (FLASH_OPTSR2_SRAM1_RST) 482 #define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */ 483 #define OB_SRAM1_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */ 484 #endif /* FLASH_OPTSR2_SRAM1_RST */ 485 /** 486 * @} 487 */ 488 489 490 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes SRAM2 Erase On Reset 491 * @{ 492 */ 493 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 494 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTSR2_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup FLASH_OB_USER_BKPRAM_ECC FLASH Option Bytes User BKPRAM ECC check 500 * @{ 501 */ 502 #define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ 503 #define OB_BKPRAM_ECC_DISABLE FLASH_OPTSR2_BKPRAM_ECC /*!< BKPRAM ECC check disable */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check 509 * @{ 510 */ 511 #if defined (FLASH_OPTSR2_SRAM3_ECC) 512 #define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ 513 #define OB_SRAM3_ECC_DISABLE FLASH_OPTSR2_SRAM3_ECC /*!< SRAM3 ECC check disable */ 514 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check 520 * @{ 521 */ 522 #define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ 523 #define OB_SRAM2_ECC_DISABLE FLASH_OPTSR2_SRAM2_ECC /*!< SRAM2 ECC check disable */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup FLASH_OB_USER_SRAM1_ECC FLASH Option Bytes User SRAM1 ECC check 529 * @{ 530 */ 531 #if defined (FLASH_OPTSR2_SRAM1_ECC) 532 #define OB_SRAM1_ECC_ENABLE 0x00000000U /*!< SRAM1 ECC check enable */ 533 #define OB_SRAM1_ECC_DISABLE FLASH_OPTSR2_SRAM1_ECC /*!< SRAM1 ECC check disable */ 534 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup OB_USER_USBPD_DIS FLASH Option Bytes USB power delivery configuration 540 * @{ 541 */ 542 #if defined (FLASH_OPTSR2_USBPD_DIS) 543 #define OB_USBPD_DIS_ENABLE 0x00000000U /*!< USB power delivery check enable */ 544 #define OB_USBPD_DIS_DISABLE FLASH_OPTSR2_USBPD_DIS /*!< USB power delivery check disable */ 545 #endif /* FLASH_OPTSR2_USBPD_DIS */ 546 /** 547 * @} 548 */ 549 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone 550 * @{ 551 */ 552 #if defined (FLASH_OPTSR2_TZEN) 553 #define OB_TZEN_DISABLE (0xC3U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security disabled */ 554 #define OB_TZEN_ENABLE (0xB4U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security enabled */ 555 #endif /* FLASH_OPTSR2_TZEN */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup FLASH_Banks FLASH Banks 561 * @{ 562 */ 563 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 564 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 565 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors 571 * @{ 572 */ 573 #if (FLASH_SECTOR_NB == 128) 574 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 575 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 576 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 577 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 578 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 579 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 580 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 581 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 582 #define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ 583 #define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ 584 #define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ 585 #define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ 586 #define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ 587 #define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ 588 #define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ 589 #define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ 590 #define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ 591 #define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ 592 #define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ 593 #define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ 594 #define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ 595 #define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ 596 #define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ 597 #define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ 598 #define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ 599 #define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ 600 #define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ 601 #define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ 602 #define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ 603 #define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ 604 #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ 605 #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ 606 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ 607 #elif (FLASH_SECTOR_NB == 32) 608 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 609 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 610 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 611 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 612 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 613 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 614 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 615 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 616 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 617 #else 618 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 619 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 620 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 621 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 622 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 623 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 624 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 625 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 626 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 627 #endif /* (FLASH_SECTOR_NB == 128) */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup FLASH_Programming_Delay FLASH Programming Delay 633 * @{ 634 */ 635 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 84 MHz or 636 below */ 637 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 84 MHz 638 and 168 MHz */ 639 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 168 MHz 640 and 250 MHz */ 641 /** 642 * @} 643 */ 644 645 /** @defgroup FLASH_OTP_Blocks FLASH OTP blocks 646 * @{ 647 */ 648 #define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ 649 #define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ 650 #define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ 651 #define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ 652 #define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ 653 #define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ 654 #define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ 655 #define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ 656 #define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ 657 #define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ 658 #define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ 659 #define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ 660 #define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ 661 #define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ 662 #define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ 663 #define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ 664 #define FLASH_OTP_BLOCK_16 0x00010000U /*!< OTP Block16 */ 665 #define FLASH_OTP_BLOCK_17 0x00020000U /*!< OTP Block17 */ 666 #define FLASH_OTP_BLOCK_18 0x00040000U /*!< OTP Block18 */ 667 #define FLASH_OTP_BLOCK_19 0x00080000U /*!< OTP Block19 */ 668 #define FLASH_OTP_BLOCK_20 0x00100000U /*!< OTP Block20 */ 669 #define FLASH_OTP_BLOCK_21 0x00200000U /*!< OTP Block21 */ 670 #define FLASH_OTP_BLOCK_22 0x00400000U /*!< OTP Block22 */ 671 #define FLASH_OTP_BLOCK_23 0x00800000U /*!< OTP Block23 */ 672 #define FLASH_OTP_BLOCK_24 0x01000000U /*!< OTP Block24 */ 673 #define FLASH_OTP_BLOCK_25 0x02000000U /*!< OTP Block25 */ 674 #define FLASH_OTP_BLOCK_26 0x04000000U /*!< OTP Block26 */ 675 #define FLASH_OTP_BLOCK_27 0x08000000U /*!< OTP Block27 */ 676 #define FLASH_OTP_BLOCK_28 0x10000000U /*!< OTP Block28 */ 677 #define FLASH_OTP_BLOCK_29 0x20000000U /*!< OTP Block29 */ 678 #define FLASH_OTP_BLOCK_30 0x40000000U /*!< OTP Block30 */ 679 #define FLASH_OTP_BLOCK_31 0x80000000U /*!< OTP Block31 */ 680 #define FLASH_OTP_BLOCK_ALL 0xFFFFFFFFU /*!< OTP All Blocks */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup FLASH_WRP_State FLASH WRP State 686 * @{ 687 */ 688 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired flash sectors */ 689 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired flash sectors */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup FLASH_OB_BOOT_CONFIG FLASH Option Bytes Boot configuration 695 * @{ 696 */ 697 #define OB_BOOT_NS 0x00000001U /*!< Non-secure boot address */ 698 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 699 #define OB_BOOT_SEC 0x00000002U /*!< Secure boot address */ 700 #endif /* __ARM_FEATURE_CMSE */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 706 * @{ 707 */ 708 #define OB_BOOT_LOCK_DISABLE 0xC3U /*!< Boot lock disable */ 709 #define OB_BOOT_LOCK_ENABLE 0xB4U /*!< Boot lock enable */ 710 /** 711 * @} 712 */ 713 714 /** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes 715 * @{ 716 */ 717 #define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ 718 #define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup FLASH_PRIV_MODE FLASH privilege mode 724 * @{ 725 */ 726 #define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged 727 or unprivileged access */ 728 #define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to 729 non-privilege access */ 730 731 #define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or 732 unprivileged access */ 733 #if defined (FLASH_PRIVCFGR_SPRIV) 734 #define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege 735 access */ 736 #endif /* FLASH_PRIVCFGR_SPRIV */ 737 /** 738 * @} 739 */ 740 741 #if defined (FLASH_SR_OBKERR) 742 /** @defgroup FLASH_OBK_SWAP_Offset FLASH OBK Swap Offset 743 * @{ 744 */ 745 #define FLASH_OBK_SWAP_OFFSET_NO_DATA 0x000U /*!< No data will be copied from current to alternate OBK */ 746 #define FLASH_OBK_SWAP_OFFSET_HDPL0 0x010U /*!< HDPL0 data will be copied from current to alternate OBK */ 747 #define FLASH_OBK_SWAP_OFFSET_HDPL1 0x090U /*!< HDPL0/1 data will be copied from current to alternate OBK */ 748 #define FLASH_OBK_SWAP_OFFSET_HDPL2 0x0C0U /*!< HDPL0/1/2 data will be copied from current to alternate OBK */ 749 #define FLASH_OBK_SWAP_OFFSET_HDPL3_S 0x180U /*!< HDPL0/1/2/3_S data will be copied from current to alternate 750 OBK */ 751 #define FLASH_OBK_SWAP_OFFSET_ALL 0x1FFU /*!< All OBK data (511) will be copied from current to alternate 752 OBK */ 753 /** 754 * @} 755 */ 756 #endif /* FLASH_SR_OBKERR */ 757 758 /** @defgroup FLASH_Operation_Type FLASH Operation Type 759 * @{ 760 */ 761 #define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ 762 #define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ 763 #if defined (FLASH_SR_OBKERR) 764 #define FLASH_OPERATION_TYPE_OBKALTERASE FLASH_OPSR_CODE_OP_1 /*!< OBK alternate sector erase 765 operation */ 766 #endif /* FLASH_SR_OBKERR */ 767 #define FLASH_OPERATION_TYPE_SECTORERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Sector erase operation */ 768 #define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ 769 #define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ 770 #define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ 771 #if defined (FLASH_SR_OBKERR) 772 #define FLASH_OPERATION_TYPE_OBKSWAP (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< OBK 773 swap operation */ 774 #endif /* FLASH_SR_OBKERR */ 775 /** 776 * @} 777 */ 778 779 /** @defgroup FLASH_Operation_Area FLASH Operation Area 780 * @{ 781 */ 782 #define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Flash Bank 1 */ 783 #define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Flash Bank 2 */ 784 #define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ 785 #if defined (FLASH_EDATAR_EDATA_EN) 786 #define FLASH_OPERATION_AREA_DATA FLASH_OPSR_DATA_OP /*!< Operation in Flash high-cycle data area */ 787 #endif /* FLASH_EDATAR_EDATA_EN */ 788 #define FLASH_OPERATION_AREA_OTP FLASH_OPSR_OTP_OP /*!< Operation in Flash OTP area */ 789 /** 790 * @} 791 */ 792 793 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 794 /** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration 795 * @{ 796 */ 797 #define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ 798 #define FLASH_INV_ENABLE FLASH_CR_INV /*!< Security state of Flash is inverted */ 799 /** 800 * @} 801 */ 802 #endif /* __ARM_FEATURE_CMSE */ 803 /** 804 * @} 805 */ 806 /* Exported macros ------------------------------------------------------------*/ 807 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros 808 * @{ 809 */ 810 811 /** 812 * @brief Enable the FLASH prefetch buffer. 813 * @retval None 814 */ 815 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 816 817 /** 818 * @brief Disable the FLASH prefetch buffer. 819 * @retval None 820 */ 821 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 822 823 /** 824 * @brief Enable the FLASH smart prefetch buffer. 825 * @retval None 826 */ 827 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 828 829 /** 830 * @brief Disable the FLASH smart prefetch buffer. 831 * @retval None 832 */ 833 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 834 835 /** 836 * @brief Set the FLASH Programming Delay. 837 * @param __DELAY__ FLASH Programming Delay 838 * This parameter can be a value of @ref FLASH_Programming_Delay 839 * @retval none 840 */ 841 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 842 843 /** 844 * @brief Get the FLASH Programming Delay. 845 * @retval FLASH Programming Delay 846 * This return value can be a value of @ref FLASH_Programming_Delay 847 */ 848 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 849 850 /** 851 * @} 852 */ 853 /* Exported functions --------------------------------------------------------*/ 854 /** @addtogroup FLASHEx_Exported_Functions 855 * @{ 856 */ 857 858 /** @addtogroup FLASHEx_Exported_Functions_Group1 859 * @{ 860 */ 861 /* Extension Erase and OB Program operation functions ******************************/ 862 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 863 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 864 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 865 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 866 #if defined (FLASH_SR_OBKERR) 867 HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void); 868 HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void); 869 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset); 870 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset); 871 #endif /* FLASH_SR_OBKERR */ 872 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); 873 /** 874 * @} 875 */ 876 877 /** @addtogroup FLASHEx_Exported_Functions_Group2 878 * @{ 879 */ 880 /* Extension Protection configuration functions *************************************/ 881 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 882 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 883 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); 884 uint32_t HAL_FLASHEx_GetPrivMode(void); 885 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 886 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); 887 uint32_t HAL_FLASHEx_GetSecInversion(void); 888 #endif /* __ARM_FEATURE_CMSE */ 889 HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef *pHDPExtension); 890 /** 891 * @} 892 */ 893 894 /** 895 * @} 896 */ 897 898 /** @addtogroup FLASHEx_Exported_Functions_Group3 899 * @{ 900 */ 901 void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); 902 void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); 903 void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); 904 void HAL_FLASHEx_ECCD_IRQHandler(void); 905 __weak void HAL_FLASHEx_EccDetectionCallback(void); 906 __weak void HAL_FLASHEx_EccCorrectionCallback(void); 907 /** 908 * @} 909 */ 910 /* Private types -------------------------------------------------------------*/ 911 /* Private variables ---------------------------------------------------------*/ 912 /* Private constants ---------------------------------------------------------*/ 913 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants 914 * @{ 915 */ 916 #define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */ 917 #define FLASH_ADDRESS_OFFSET_OTP (0x00000600U) /*!< Flash address offset of OTP area */ 918 #define FLASH_ADDRESS_OFFSET_EDATA (0x0000F000U) /*!< Flash address offset of EDATA area */ 919 /** 920 * @} 921 */ 922 /* Private macros ------------------------------------------------------------*/ 923 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 924 * @{ 925 */ 926 927 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 928 * @{ 929 */ 930 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 931 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 932 ((VALUE) == FLASH_TYPEERASE_SECTORS_NS) || \ 933 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 934 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS) || \ 935 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 936 #else 937 #if defined (FLASH_SR_OBKERR) 938 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 939 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 940 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 941 #else 942 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 943 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 944 #endif /* FLASH_SR_OBKERR */ 945 #endif /* __ARM_FEATURE_CMSE */ 946 947 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 948 ((VALUE) == OB_WRPSTATE_ENABLE)) 949 950 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ 951 (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) 952 953 #define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) || \ 954 ((STATE) == OB_PROD_STATE_PROVISIONING) || \ 955 ((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \ 956 ((STATE) == OB_PROD_STATE_TZ_CLOSED) || \ 957 ((STATE) == OB_PROD_STATE_CLOSED) || \ 958 ((STATE) == OB_PROD_STATE_LOCKED) || \ 959 ((STATE) == OB_PROD_STATE_REGRESSION) || \ 960 ((STATE) == OB_PROD_STATE_NS_REGRESSION)) 961 962 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_1) || ((LEVEL) == OB_BOR_LEVEL_2) || \ 963 ((LEVEL) == OB_BOR_LEVEL_3)) 964 965 #define IS_OB_USER_BORH_EN(VALUE) (((VALUE) == OB_BORH_DISABLE) || ((VALUE) == OB_BORH_ENABLE)) 966 967 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 968 969 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 970 971 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 972 973 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 974 975 #define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || \ 976 ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) 977 978 #define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || \ 979 ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) 980 981 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 982 983 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 984 985 #define IS_OB_USER_BOOT_UBE(VALUE) (((VALUE) == OB_UBE_OEM_IROT) || ((VALUE) == OB_UBE_ST_IROT)) 986 987 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 988 989 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 990 #define IS_OB_USER_SRAM1_3_RST(VALUE) (((VALUE) == OB_SRAM1_3_RST_ERASE) || ((VALUE) == OB_SRAM1_3_RST_NOT_ERASE)) 991 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 992 993 #if defined (FLASH_OPTSR2_SRAM1_RST) 994 #define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) 995 #endif /* FLASH_OPTSR2_SRAM1_RST */ 996 997 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 998 999 #define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) 1000 1001 #if defined (FLASH_OPTSR2_SRAM3_ECC) 1002 #define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) 1003 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 1004 1005 #if defined (FLASH_OPTSR2_SRAM1_ECC) 1006 #define IS_OB_USER_SRAM1_ECC(VALUE) (((VALUE) == OB_SRAM1_ECC_ENABLE) || ((VALUE) == OB_SRAM1_ECC_DISABLE)) 1007 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 1008 1009 #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) 1010 1011 #if defined(FLASH_OPTSR2_USBPD_DIS) 1012 #define IS_OB_USER_USBPD_DIS(VALUE) (((VALUE) == OB_USBPD_DIS_ENABLE) || ((VALUE) == OB_USBPD_DIS_DISABLE)) 1013 #endif /* FLASH_OPTSR2_USBPD_DIS */ 1014 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1015 1016 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ 1017 (((TYPE) & ~OB_USER_ALL) == 0U)) 1018 1019 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1020 #define IS_OB_BOOT_CONFIG(CFG) (((CFG) == OB_BOOT_NS) || ((CFG) == OB_BOOT_SEC)) 1021 #else 1022 #define IS_OB_BOOT_CONFIG(CFG) ((CFG) == OB_BOOT_NS) 1023 #endif /* __ARM_FEATURE_CMSE */ 1024 1025 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1026 1027 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1028 #define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || ((CFG) == FLASH_BB_PRIV)) 1029 #else 1030 #define IS_FLASH_BB_EXCLUSIVE(CFG) ((CFG) == FLASH_BB_PRIV) 1031 #endif /* __ARM_FEATURE_CMSE */ 1032 1033 #define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) 1034 1035 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1036 #define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || ((CFG) == FLASH_INV_ENABLE)) 1037 #endif /* __ARM_FEATURE_CMSE */ 1038 1039 #define IS_FLASH_EDATA_SIZE(SECTOR) ((SECTOR) <= FLASH_EDATA_SECTOR_NB) 1040 /** 1041 * @} 1042 */ 1043 1044 /** 1045 * @} 1046 */ 1047 /* Private functions ---------------------------------------------------------*/ 1048 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 1049 * @{ 1050 */ 1051 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks); 1052 /** 1053 * @} 1054 */ 1055 1056 /** 1057 * @} 1058 */ 1059 1060 /** 1061 * @} 1062 */ 1063 1064 /** 1065 * @} 1066 */ 1067 1068 #ifdef __cplusplus 1069 } 1070 #endif 1071 1072 #endif /* STM32H5xx_HAL_FLASH_EX_H */ 1073
