1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_FLASH_H 21 #define STM32WBAxx_HAL_FLASH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASH 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASH_Exported_Types FLASH Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Mass erase or page erase. 49 This parameter can be a value of @ref FLASH_Type_Erase */ 50 uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled 51 This parameter must be a value between 0 and (max number of pages - 1) */ 52 uint32_t NbPages; /*!< Number of pages to be erased. 53 This parameter must be a value between 1 and (max number of pages - value of initial page)*/ 54 } FLASH_EraseInitTypeDef; 55 56 /** 57 * @brief FLASH Option Bytes Program structure definition 58 */ 59 typedef struct 60 { 61 uint32_t OptionType; /*!< Option byte to be configured. 62 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 63 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 64 Only one WRP area could be programmed at the same time. 65 This parameter can be value of @ref FLASH_OB_WRP_Area */ 66 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 67 This parameter must be a value between 0 and (max number of pages - 1) */ 68 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 69 This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ 70 FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). 71 This parameter can be set to ENABLE or DISABLE */ 72 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 73 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 74 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 75 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 76 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 77 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 78 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 79 @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_IWDG_SW, 80 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SRAM2_PAR, 82 @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_nSWBOOT0, 83 @ref FLASH_OB_USER_nBOOT0 and @ref FLASH_OB_USER_TZEN */ 84 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 85 uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). 86 This parameter must be a value of @ref FLASH_OB_WMSEC */ 87 uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). 88 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 89 uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). 90 This parameter must be a value between WMSecStartPage and (max number of pages in the bank - 1) */ 91 uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). 92 This parameter must be a value between WMSecStartPage and WMSecEndPage */ 93 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 94 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 95 #endif /* __ARM_FEATURE_CMSE */ 96 uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). 97 This parameter must be a value of @ref FLASH_OB_BOOTADDR */ 98 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 99 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 100 uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). 101 This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ 102 uint32_t RDPKey1; /*!< Value of the RDP OEM key - bits[0:31] (used for OPTIONBYTE_RDPKEY) */ 103 uint32_t RDPKey2; /*!< Value of the RDP OEM key - bits[32:63] (used for OPTIONBYTE_RDPKEY) */ 104 } FLASH_OBProgramInitTypeDef; 105 106 /** 107 * @brief FLASH handle Structure definition 108 */ 109 typedef struct 110 { 111 HAL_LockTypeDef Lock; /*!< FLASH locking object */ 112 uint32_t ErrorCode; /*!< FLASH error code */ 113 uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 114 uint32_t Address; /*!< Internal variable to save address selected for program in IT context */ 115 uint32_t Page; /*!< Internal variable to define the current page which is erasing in IT context */ 116 uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */ 117 } FLASH_ProcessTypeDef; 118 119 /** 120 * @} 121 */ 122 123 /* Exported constants --------------------------------------------------------*/ 124 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 125 * @{ 126 */ 127 128 /** @defgroup FLASH_Flags FLASH Flags Definition 129 * @{ 130 */ 131 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 132 #define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ 133 #define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ 134 #define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ 135 #define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ 136 #define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ 137 #define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ 138 #define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ 139 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 140 #define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ 141 #define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ 142 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 143 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 144 145 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 146 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) /*!< Flash all flags from Status Register */ 147 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 148 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 149 #else 150 #define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ 151 #define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ 152 #define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ 153 #define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ 154 #define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ 155 #define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ 156 #define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ 157 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 158 #define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ 159 #define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ 160 #define FLASH_FLAG_OEM1LOCK FLASH_NSSR_OEM1LOCK /*!< FLASH OEM1 key RDP lock flag */ 161 #define FLASH_FLAG_OEM2LOCK FLASH_NSSR_OEM2LOCK /*!< FLASH OEM2 key RDP lock flag */ 162 #define FLASH_FLAG_PD FLASH_NSSR_PD /*!< FLASH in power-down lock flag */ 163 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 164 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 165 166 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 167 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 168 FLASH_FLAG_OPTWERR) /*!< Flash all flags from Status Register */ 169 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 170 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 171 #endif /* __ARM_FEATURE_CMSE */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 177 * @brief FLASH Interrupt definition 178 * @{ 179 */ 180 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 181 #define FLASH_IT_EOP FLASH_SECCR1_EOPIE /*!< End of FLASH Operation Interrupt source */ 182 #define FLASH_IT_OPERR FLASH_SECCR1_ERRIE /*!< Error Interrupt source */ 183 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> FLASH_ECCR_ECCIE_Pos) /*!< ECC Correction Interrupt source */ 184 #else 185 #define FLASH_IT_EOP FLASH_NSCR1_EOPIE /*!< End of FLASH Operation Interrupt source */ 186 #define FLASH_IT_OPERR FLASH_NSCR1_ERRIE /*!< Error Interrupt source */ 187 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> FLASH_ECCR_ECCIE_Pos) /*!< ECC Correction Interrupt source */ 188 #endif /* __ARM_FEATURE_CMSE */ 189 /** 190 * @} 191 */ 192 193 /** @defgroup FLASH_Error FLASH Error 194 * @{ 195 */ 196 #define HAL_FLASH_ERROR_NONE 0x00000000U /*!< Flash no error */ 197 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR /*!< Flash operation error */ 198 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR /*!< Flash programming error */ 199 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Flash write protection error */ 200 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR /*!< Flash programming alignment error */ 201 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR /*!< Flash size error */ 202 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Flash programming sequence error */ 203 #define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR /*!< Flash option modification error */ 204 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< Flash ECC correction error */ 205 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< Flash ECC detection error */ 206 /** 207 * @} 208 */ 209 210 /** @defgroup FLASH_Type_Erase FLASH Erase Type 211 * @{ 212 */ 213 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 214 #define FLASH_TYPEERASE_PAGES FLASH_SECCR1_PER /*!< Secure pages erase activation */ 215 #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR1_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase activation */ 216 #define FLASH_TYPEERASE_MASSERASE FLASH_SECCR1_MER /*!< Secure flash mass erase activation */ 217 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ 218 #else 219 #define FLASH_TYPEERASE_PAGES FLASH_NSCR1_PER /*!< Pages erase activation */ 220 #define FLASH_TYPEERASE_MASSERASE FLASH_NSCR1_MER /*!< Flash mass erase activation */ 221 #endif /* __ARM_FEATURE_CMSE */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup FLASH_Banks FLASH Banks 227 * @{ 228 */ 229 #define FLASH_BANK_1 FLASH_NSCR1_MER /*!< Bank 1 */ 230 #define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type 236 * @{ 237 */ 238 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 239 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR1_PG /*!< Program a quad-word (128-bit) at a specified secure address */ 240 #define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR1_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) at a specified non-secure address */ 241 #define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR1_PG | FLASH_SECCR1_BWR) /*!< Program a burst (8xquad-word) at a specified secure address */ 242 #define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR1_PG | FLASH_NSCR1_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst (8xquad-word) at a specified non-secure address */ 243 #else 244 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR1_PG /*!< Program a quad-word (128-bit) at a specified address */ 245 #define FLASH_TYPEPROGRAM_BURST (FLASH_NSCR1_PG | FLASH_NSCR1_BWR) /*!< Program a burst (8xquad-word) at a specified address */ 246 #endif /* __ARM_FEATURE_CMSE */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 252 * @{ 253 */ 254 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 255 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 256 #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ 257 #define OPTIONBYTE_BOOTADDR 0x00000008U /*!< Boot address option byte configuration */ 258 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 259 #define OPTIONBYTE_WMSEC 0x00000010U /*!< Watermark-based secure area option byte configuration */ 260 #define OPTIONBYTE_BOOT_LOCK 0x00000020U /*!< Boot lock option byte configuration */ 261 #endif /* __ARM_FEATURE_CMSE */ 262 #define OPTIONBYTE_RDPKEY 0x00000040U /*!< RDP Key option byte configuration */ 263 /** 264 * @} 265 */ 266 267 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 268 * @{ 269 */ 270 #define OB_WRPAREA_BANK1_AREAA 0x00000001U /*!< Flash Area A */ 271 #define OB_WRPAREA_BANK1_AREAB 0x00000002U /*!< Flash Area B */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 277 * @{ 278 */ 279 #define OB_RDP_LEVEL_0 0xAAU /*!< RDP level 0 code */ 280 #define OB_RDP_LEVEL_0_5 0x55U /*!< RDP level 0.5 code */ 281 #define OB_RDP_LEVEL_1 0xBBU /*!< RDP level 1 code */ 282 #define OB_RDP_LEVEL_2 0xCCU /*!< RDP level 2 code. 283 Warning: When enabling read protection level 2 284 it's no more possible to go back to level 1 or 0. */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup FLASH_OB_RDP_Key_Type FLASH Option Bytes Read Protection Key Type 290 * @{ 291 */ 292 #define OB_RDP_KEY_OEM1 0x01U /*!< OEM1 key */ 293 #define OB_RDP_KEY_OEM2 0x02U /*!< OEM2 key */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 299 * @{ 300 */ 301 #define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ 302 #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ 303 #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ 304 #define OB_USER_SRAM1_RST FLASH_OPTR_SRAM1_RST /*!< SRAM1 erase upon system reset */ 305 #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ 306 #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ 307 #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ 308 #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ 309 #define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity error enable */ 310 #define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 Erase when system reset */ 311 #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ 312 #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ 313 #if defined(FLASH_OPTR_TZEN) 314 #define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone enable */ 315 #endif /* FLASH_OPTR_TZEN */ 316 317 #if defined(FLASH_OPTR_TZEN) 318 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 319 OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 320 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SRAM2_PE | \ 321 OB_USER_SRAM2_RST | OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | \ 322 OB_USER_TZEN) /*!< All User option bits */ 323 #else 324 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 325 OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 326 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SRAM2_PE | \ 327 OB_USER_SRAM2_RST | OB_USER_nSWBOOT0 | OB_USER_nBOOT0) /*!< All User option bits */ 328 #endif /* FLASH_OPTR_TZEN */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 334 * @{ 335 */ 336 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ 337 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */ 338 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */ 339 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ 340 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 346 * @{ 347 */ 348 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 349 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 355 * @{ 356 */ 357 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 358 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes User SRAM1 Erase On Reset Type 364 * @{ 365 */ 366 #define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */ 367 #define OB_SRAM1_RST_NOT_ERASE FLASH_OPTR_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 373 * @{ 374 */ 375 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 376 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 382 * @{ 383 */ 384 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 385 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 386 /** 387 * @} 388 */ 389 390 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 391 * @{ 392 */ 393 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 394 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 395 /** 396 * @} 397 */ 398 399 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 400 * @{ 401 */ 402 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 403 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 404 /** 405 * @} 406 */ 407 408 409 /** @defgroup FLASH_OB_USER_SRAM2_PAR FLASH Option Bytes User SRAM2 Parity error enable 410 * @{ 411 */ 412 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ 413 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check disable */ 414 /** 415 * @} 416 */ 417 418 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 419 * @{ 420 */ 421 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 422 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 423 /** 424 * @} 425 */ 426 427 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 428 * @{ 429 */ 430 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 431 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from BOOT0 pin */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 437 * @{ 438 */ 439 #define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 440 #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 441 /** 442 * @} 443 */ 444 445 446 447 #if defined(FLASH_OPTR_TZEN) 448 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone 449 * @{ 450 */ 451 #define OB_TZEN_DISABLE 0x00000000U /*!< Global TrustZone security disabled */ 452 #define OB_TZEN_ENABLE FLASH_OPTR_TZEN /*!< Global TrustZone security enabled */ 453 /** 454 * @} 455 */ 456 #endif /* FLASH_OPTR_TZEN */ 457 458 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 459 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 460 * @{ 461 */ 462 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */ 463 #define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup FLASH_OB_WMSEC FLASH Option Bytes Watermarked-based security configuration 469 * @{ 470 */ 471 #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ 472 473 #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ 474 #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ 475 #define OB_WMSEC_HDP_AREA_ENABLE 0x00000080U /*!< Enable Watermarked-based secure hide area */ 476 #define OB_WMSEC_HDP_AREA_DISABLE 0x00000100U /*!< Disable Watermarked-based secure hide area */ 477 /** 478 * @} 479 */ 480 #endif /* __ARM_FEATURE_CMSE */ 481 482 /** @defgroup FLASH_OB_BOOTADDR FLASH Option Bytes Boot address 483 * @{ 484 */ 485 #define OB_BOOTADDR_NS0 0x00000001U /*!< Non-secure boot address 0 */ 486 #define OB_BOOTADDR_NS1 0x00000002U /*!< Non-secure boot address 1 */ 487 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 488 #define OB_BOOTADDR_SEC0 0x00000004U /*!< Secure boot address 0 */ 489 #endif /* __ARM_FEATURE_CMSE */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup FLASH_Latency FLASH Latency 495 * @{ 496 */ 497 #define FLASH_LATENCY_0 0U /*!< FLASH Zero wait state */ 498 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ 499 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ 500 #define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */ 501 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_2 /*!< FLASH Four wait states */ 502 #define FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Five wait state */ 503 #define FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Six wait state */ 504 #define FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states */ 505 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_3 /*!< FLASH Eight wait states */ 506 #define FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0) /*!< FLASH Nine wait states */ 507 #define FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1) /*!< FLASH Ten wait state */ 508 #define FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Eleven wait state */ 509 #define FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2) /*!< FLASH Twelve wait states */ 510 #define FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Thirteen wait states */ 511 #define FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Fourteen wait states */ 512 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY /*!< FLASH Fifteen wait states */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup FLASH_Keys FLASH Keys 518 * @{ 519 */ 520 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 521 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 522 to unlock the FLASH registers access */ 523 524 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 525 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 526 to unlock the PDREQ bit in FLASH_ACR */ 527 528 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 529 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 530 to allow option bytes operations */ 531 /** 532 * @} 533 */ 534 535 /** 536 * @} 537 */ 538 539 /* Exported macros -----------------------------------------------------------*/ 540 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 541 * @brief macros to control FLASH features 542 * @{ 543 */ 544 545 /** 546 * @brief Set the FLASH Latency. 547 * @param __LATENCY__ FLASH Latency. 548 * This parameter can be one of the following values : 549 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 550 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 551 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 552 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 553 * @arg @ref FLASH_LATENCY_4 FLASH Four wait states 554 * @arg @ref FLASH_LATENCY_5 FLASH Five wait states 555 * @arg @ref FLASH_LATENCY_6 FLASH Six wait states 556 * @arg @ref FLASH_LATENCY_7 FLASH Seven wait states 557 * @arg @ref FLASH_LATENCY_8 FLASH Eight wait states 558 * @arg @ref FLASH_LATENCY_9 FLASH Nine wait states 559 * @arg @ref FLASH_LATENCY_10 FLASH Ten wait states 560 * @arg @ref FLASH_LATENCY_11 FLASH Eleven wait states 561 * @arg @ref FLASH_LATENCY_12 FLASH Twelve wait states 562 * @arg @ref FLASH_LATENCY_13 FLASH Thirteen wait states 563 * @arg @ref FLASH_LATENCY_14 FLASH Fourteen wait states 564 * @arg @ref FLASH_LATENCY_15 FLASH Fifteen wait states 565 * @retval None 566 */ 567 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 568 569 /** 570 * @brief Get the FLASH Latency. 571 * @retval FLASH Latency 572 * Returned value can be one of the following values : 573 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 574 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 575 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 576 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 577 * @arg @ref FLASH_LATENCY_4 FLASH Four wait states 578 * @arg @ref FLASH_LATENCY_5 FLASH Five wait states 579 * @arg @ref FLASH_LATENCY_6 FLASH Six wait states 580 * @arg @ref FLASH_LATENCY_7 FLASH Seven wait states 581 * @arg @ref FLASH_LATENCY_8 FLASH Eight wait states 582 * @arg @ref FLASH_LATENCY_9 FLASH Nine wait states 583 * @arg @ref FLASH_LATENCY_10 FLASH Ten wait states 584 * @arg @ref FLASH_LATENCY_11 FLASH Eleven wait states 585 * @arg @ref FLASH_LATENCY_12 FLASH Twelve wait states 586 * @arg @ref FLASH_LATENCY_13 FLASH Thirteen wait states 587 * @arg @ref FLASH_LATENCY_14 FLASH Fourteen wait states 588 * @arg @ref FLASH_LATENCY_15 FLASH Fifteen wait states 589 */ 590 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 591 592 /** 593 * @brief Enable the FLASH prefetch buffer. 594 * @retval None 595 */ 596 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 597 598 /** 599 * @brief Disable the FLASH prefetch buffer. 600 * @retval None 601 */ 602 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 603 604 /** 605 * @brief Enable the FLASH power down during Low-Power sleep mode 606 * @retval None 607 */ 608 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 609 610 /** 611 * @brief Disable the FLASH power down during Low-Power sleep mode 612 * @retval None 613 */ 614 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 615 616 /** 617 * @} 618 */ 619 620 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 621 * @brief macros to handle FLASH interrupts 622 * @{ 623 */ 624 625 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 626 /** 627 * @brief Enable secure FLASH interrupts from the secure world. 628 * @param __INTERRUPT__ FLASH interrupt 629 * This parameter can be any combination of the following values: 630 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 631 * @arg @ref FLASH_IT_OPERR Error Interrupt 632 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 633 * @retval None 634 */ 635 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 636 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 637 } while(0) 638 /** 639 * @brief Enable non-secure FLASH interrupts from the secure world. 640 * @param __INTERRUPT__ FLASH interrupt. 641 * This parameter can be any combination of the following values: 642 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 643 * @arg @ref FLASH_IT_OPERR Error Interrupt 644 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 645 * @retval None 646 */ 647 #define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 648 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 649 } while(0) 650 #else 651 /** 652 * @brief Enable non-secure FLASH interrupts from the non-secure world. 653 * @param __INTERRUPT__ FLASH interrupt. 654 * This parameter can be any combination of the following values: 655 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 656 * @arg @ref FLASH_IT_OPERR Error Interrupt 657 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 658 * @retval None 659 */ 660 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 661 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 662 } while(0) 663 #endif /* __ARM_FEATURE_CMSE */ 664 665 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 666 /** 667 * @brief Disable secure FLASH interrupts from the secure world. 668 * @param __INTERRUPT__ FLASH interrupt. 669 * This parameter can be any combination of the following values: 670 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 671 * @arg @ref FLASH_IT_OPERR Error Interrupt 672 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 673 * @retval None 674 */ 675 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 676 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->SECCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 677 } while(0) 678 /** 679 * @brief Disable non-secure FLASH interrupts from the secure world. 680 * @param __INTERRUPT__ FLASH interrupt. 681 * This parameter can be any combination of the following values: 682 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 683 * @arg @ref FLASH_IT_OPERR Error Interrupt 684 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 685 * @retval None 686 */ 687 #define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 688 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 689 } while(0) 690 #else 691 /** 692 * @brief Disable non-secure FLASH interrupts from the non-secure world. 693 * @param __INTERRUPT__ FLASH interrupt. 694 * This parameter can be any combination of the following values: 695 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 696 * @arg @ref FLASH_IT_OPERR Error Interrupt 697 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 698 * @retval None 699 */ 700 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 701 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 702 } while(0) 703 #endif /* __ARM_FEATURE_CMSE */ 704 705 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 706 /** 707 * @brief Check whether the specified secure FLASH flags from the secure world is set or not. 708 * @param __FLAG__ specifies the FLASH flag to check. 709 * This parameter can be one of the following values: 710 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 711 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 712 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 713 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 714 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 715 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 716 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 717 * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag 718 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 719 * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag 720 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 721 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 722 * @retval The new state of FLASH_FLAG (SET or RESET). 723 */ 724 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 725 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 726 ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ 727 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ 728 (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) 729 /** 730 * @brief Check whether the specified non-secure FLASH flags from the secure world is set or not. 731 * @param __FLAG__ specifies the FLASH flag to check. 732 * This parameter can be one of the following values: 733 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 734 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 735 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 736 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 737 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 738 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 739 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 740 * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag 741 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 742 * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag 743 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 744 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 745 * @retval The new state of FLASH_FLAG (SET or RESET). 746 */ 747 #define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 748 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 749 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 750 #else 751 /** 752 * @brief Check whether the specified non-secure FLASH flags from the non-secure world is set or not. 753 * @param __FLAG__ specifies the FLASH flag to check. 754 * This parameter can be one of the following values: 755 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 756 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 757 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 758 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 759 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 760 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 761 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 762 * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag 763 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 764 * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag 765 * @arg @ref FLASH_FLAG_OEM1LOCK FLASH OEM1 key RDP lock flag 766 * @arg @ref FLASH_FLAG_OEM2LOCK FLASH OEM2 key RDP lock flag 767 * @arg @ref FLASH_FLAG_PD FLASH in power-down lock flag 768 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 769 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 770 * @retval The new state of FLASH_FLAG (SET or RESET). 771 */ 772 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 773 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 774 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 775 #endif /* __ARM_FEATURE_CMSE */ 776 777 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 778 /** 779 * @brief Clear secure FLASH flags from the secure world. 780 * @param __FLAG__ specifies the FLASH flags to clear. 781 * This parameter can be any combination of the following values: 782 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 783 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 784 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 785 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 786 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 787 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 788 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 789 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 790 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 791 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 792 * @retval None 793 */ 794 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 795 if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ 796 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR)) != 0U) { WRITE_REG(FLASH->SECSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); } \ 797 } while(0) 798 /** 799 * @brief Clear non-secure FLASH flags from the secure world. 800 * @param __FLAG__ specifies the FLASH flags to clear. 801 * This parameter can be any combination of the following values: 802 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 803 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 804 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 805 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 806 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 807 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 808 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 809 * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag 810 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 811 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 812 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 813 * @retval None 814 */ 815 #define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 816 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 817 } while(0) 818 #else 819 /** 820 * @brief Clear non-secure FLASH flags from the non-secure world. 821 * @param __FLAG__ specifies the FLASH flags to clear. 822 * This parameter can be any combination of the following values: 823 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 824 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 825 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 826 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 827 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 828 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 829 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 830 * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag 831 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 832 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 833 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 834 * @retval None 835 */ 836 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 837 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 838 } while(0) 839 #endif /* __ARM_FEATURE_CMSE */ 840 /** 841 * @} 842 */ 843 844 /* Include FLASH HAL Extended module */ 845 #include "stm32wbaxx_hal_flash_ex.h" 846 847 848 /* Exported functions --------------------------------------------------------*/ 849 /** @addtogroup FLASH_Exported_Functions 850 * @{ 851 */ 852 853 /* Program operation functions ***********************************************/ 854 /** @addtogroup FLASH_Exported_Functions_Group1 855 * @{ 856 */ 857 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 858 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 859 /* FLASH IRQ handler method */ 860 void HAL_FLASH_IRQHandler(void); 861 /* Callbacks in non blocking modes */ 862 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 863 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 864 /** 865 * @} 866 */ 867 868 /* Peripheral Control functions **********************************************/ 869 /** @addtogroup FLASH_Exported_Functions_Group2 870 * @{ 871 */ 872 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 873 HAL_StatusTypeDef HAL_FLASH_Lock(void); 874 /* Option bytes control */ 875 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 876 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 877 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 878 /** 879 * @} 880 */ 881 882 /* Peripheral State functions ************************************************/ 883 /** @addtogroup FLASH_Exported_Functions_Group3 884 * @{ 885 */ 886 uint32_t HAL_FLASH_GetError(void); 887 /** 888 * @} 889 */ 890 891 /** 892 * @} 893 */ 894 895 /* Private variables ---------------------------------------------------------*/ 896 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 897 * @{ 898 */ 899 extern FLASH_ProcessTypeDef pFlash; 900 /** 901 * @} 902 */ 903 904 /* Private function ----------------------------------------------------------*/ 905 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 906 * @{ 907 */ 908 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 909 /** 910 * @} 911 */ 912 913 /* Private constants ---------------------------------------------------------*/ 914 /** @defgroup FLASH_Private_Constants FLASH Private Constants 915 * @{ 916 */ 917 #define FLASH_BANK_SIZE FLASH_SIZE 918 #define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ 919 920 #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) 921 922 #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ 923 924 #define FLASH_NON_SECURE_MASK 0x80000000U 925 /** 926 * @} 927 */ 928 929 /* Private macros ------------------------------------------------------------*/ 930 /** @defgroup FLASH_Private_Macros FLASH Private Macros 931 * @{ 932 */ 933 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 934 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 935 ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ 936 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 937 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) 938 #else 939 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 940 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 941 #endif /* __ARM_FEATURE_CMSE */ 942 943 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 944 945 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 946 947 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 948 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 949 ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ 950 ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ 951 ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) 952 #else 953 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 954 ((VALUE) == FLASH_TYPEPROGRAM_BURST)) 955 #endif /* __ARM_FEATURE_CMSE */ 956 957 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 958 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ 959 (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) 960 #else 961 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 962 #endif /* __ARM_FEATURE_CMSE */ 963 964 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) 965 966 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 967 968 #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) 969 970 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 971 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 972 OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ 973 OPTIONBYTE_RDPKEY))) 974 #else 975 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 976 OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) 977 #endif /* __ARM_FEATURE_CMSE */ 978 979 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 980 981 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 982 ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ 983 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 984 ((LEVEL) == OB_RDP_LEVEL_2)) 985 986 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0x00U) && (((TYPE) & ~OB_USER_ALL) == 0x00U)) 987 988 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 989 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 990 ((LEVEL) == OB_BOR_LEVEL_4)) 991 992 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 993 994 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 995 996 #define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) 997 998 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 999 1000 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 1001 1002 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 1003 1004 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 1005 1006 1007 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 1008 1009 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 1010 1011 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 1012 1013 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) 1014 1015 1016 1017 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1018 1019 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1020 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1021 1022 #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x1B4U) != 0U) && (((CFG) & 0x4U) != 0U) && (((CFG) & 0xFFFFFE4BU) == 0U)) 1023 1024 #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((WMSEC) & OB_WMSEC_AREA1) != 0U) 1025 #endif /* __ARM_FEATURE_CMSE */ 1026 1027 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1028 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ 1029 ((CFG) == OB_BOOTADDR_SEC0)) 1030 #else 1031 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) 1032 #endif /* __ARM_FEATURE_CMSE */ 1033 1034 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 1035 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 1036 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1037 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1038 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1039 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1040 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1041 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1042 1043 #define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ 1044 ((TYPE) == OB_RDP_KEY_OEM2)) 1045 1046 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1047 #define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) 1048 #else 1049 #define IS_FLASH_SECURE_OPERATION() (0U) 1050 #endif /* __ARM_FEATURE_CMSE */ 1051 /** 1052 * @} 1053 */ 1054 1055 /** 1056 * @} 1057 */ 1058 1059 /** 1060 * @} 1061 */ 1062 1063 #ifdef __cplusplus 1064 } 1065 #endif 1066 1067 #endif /* STM32WBAxx_HAL_FLASH_H */ 1068
