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Searched refs:FDCAN_XIDFC_FLESA_Pos (Results 1 – 25 of 45) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_fdcan.c4948 MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); in FDCAN_CalcultateRamBlockAddresses()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_fdcan.c6106 MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); in FDCAN_CalcultateRamBlockAddresses()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_fdcan.c6106 MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); in FDCAN_CalcultateRamBlockAddresses()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h4436 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4437 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h7b0xx.h4571 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4572 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h7b0xxq.h4572 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4573 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h7a3xxq.h4437 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4438 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h7b3xx.h4571 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4572 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h7b3xxq.h4572 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4573 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h730xxq.h4806 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4807 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h733xx.h4805 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4806 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h725xx.h4671 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4672 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h730xx.h4805 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4806 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h735xx.h4806 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4807 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h742xx.h4458 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4459 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h723xx.h4670 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4671 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h750xx.h4629 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4630 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h753xx.h4629 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4630 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h745xx.h4660 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4661 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h745xg.h4660 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4661 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h743xx.h4553 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4554 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h755xx.h4736 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4737 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h757xx.h4819 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4820 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h747xg.h4743 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4744 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
Dstm32h747xx.h4743 #define FDCAN_XIDFC_FLESA_Pos (2U) macro
4744 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */

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