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Searched refs:ETH_MACMIIAR_CR_Div42 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_eth.c304 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/Legacy/
Dstm32f7xx_hal_eth.c303 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/Legacy/
Dstm32f4xx_hal_eth.c307 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_eth.c2361 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_eth.c2361 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h12409 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f217xx.h12664 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h12953 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f427xx.h14149 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f417xx.h13233 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f429xx.h14505 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f439xx.h14799 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f437xx.h14451 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f469xx.h17521 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f479xx.h17818 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h15402 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f745xx.h14761 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f756xx.h15402 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f746xx.h15109 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f765xx.h15395 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f777xx.h16082 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f767xx.h15789 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f779xx.h16177 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro
Dstm32f769xx.h15884 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; … macro