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Searched refs:ETH_MACMIIAR_CR_Div26 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_eth.c299 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/Legacy/
Dstm32f7xx_hal_eth.c298 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/Legacy/
Dstm32f4xx_hal_eth.c302 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_eth.c2356 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_eth.c2356 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h12418 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f217xx.h12673 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h12962 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f427xx.h14158 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f417xx.h13242 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f429xx.h14514 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f439xx.h14808 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f437xx.h14460 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f469xx.h17530 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f479xx.h17827 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h15411 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f745xx.h14770 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f756xx.h15411 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f746xx.h15118 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f765xx.h15404 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f777xx.h16091 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f767xx.h15798 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f779xx.h16186 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro
Dstm32f769xx.h15893 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; … macro