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Searched refs:ETH_MACMIIAR_CR_Div16 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_eth.c294 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/Legacy/
Dstm32f7xx_hal_eth.c293 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/Legacy/
Dstm32f4xx_hal_eth.c297 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_eth.c2351 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_eth.c2351 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_SetMDIOClockRange()
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f207xx.h12415 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f217xx.h12670 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f407xx.h12959 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f427xx.h14155 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f417xx.h13239 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f429xx.h14511 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f439xx.h14805 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f437xx.h14457 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f469xx.h17527 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f479xx.h17824 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h15408 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f745xx.h14767 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f756xx.h15408 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f746xx.h15115 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f765xx.h15401 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f777xx.h16088 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f767xx.h15795 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f779xx.h16183 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro
Dstm32f769xx.h15890 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; … macro