Searched refs:ETH_MACMDIOAR_CR_DIV42 (Results 1 – 25 of 55) sorted by relevance
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2077 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in HAL_ETH_SetMDIOClockRange()2628 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in ETH_MAC_MDIO_ClkConfig()
2412 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in HAL_ETH_SetMDIOClockRange()
2468 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in HAL_ETH_SetMDIOClockRange()
2430 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in HAL_ETH_SetMDIOClockRange()
2579 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; in HAL_ETH_SetMDIOClockRange()
6330 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
6854 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
6775 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
6407 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
7912 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7911 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7658 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7384 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7657 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7672 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7586 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7479 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7779 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
7862 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
6803 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
6394 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
