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Searched refs:ETH_DMAC0TXCR_TCW_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h14876 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
14877 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14879 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14880 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14881 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151fxx_cm4.h15039 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
15040 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15042 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15043 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15044 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151axx_ca7.h14876 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
14877 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14879 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14880 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14881 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151axx_cm4.h14842 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
14843 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14845 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14846 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14847 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151dxx_cm4.h14842 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
14843 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14845 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14846 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
14847 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151cxx_ca7.h15073 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
15074 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15076 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15077 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15078 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151cxx_cm4.h15039 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
15040 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15042 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15043 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15044 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp151fxx_ca7.h15073 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
15074 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15076 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15077 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
15078 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153axx_ca7.h16427 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16428 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16430 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16431 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16432 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153axx_cm4.h16393 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16394 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16396 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16397 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16398 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153cxx_ca7.h16624 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16625 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16627 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16628 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16629 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153cxx_cm4.h16590 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16591 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16593 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16594 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16595 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153dxx_ca7.h16427 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16428 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16430 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16431 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16432 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153dxx_cm4.h16393 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16394 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16396 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16397 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16398 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153fxx_ca7.h16624 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16625 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16627 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16628 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16629 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp153fxx_cm4.h16590 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16591 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16593 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16594 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16595 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157axx_ca7.h16542 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16543 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16545 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16546 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16547 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157axx_cm4.h16508 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16509 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16511 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16512 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16513 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157cxx_ca7.h16739 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16740 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16742 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16743 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16744 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157cxx_cm4.h16705 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16706 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16708 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16709 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16710 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157dxx_ca7.h16542 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16543 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16545 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16546 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16547 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157dxx_cm4.h16508 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16509 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16511 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16512 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16513 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157fxx_ca7.h16739 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16740 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16742 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16743 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16744 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…
Dstm32mp157fxx_cm4.h16705 #define ETH_DMAC0TXCR_TCW_Pos (1U) macro
16706 #define ETH_DMAC0TXCR_TCW_Msk (0x7UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16708 #define ETH_DMAC0TXCR_TCW_0 (0x1UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16709 #define ETH_DMAC0TXCR_TCW_1 (0x2UL << ETH_DMAC0TXCR_TCW_Pos) /*…
16710 #define ETH_DMAC0TXCR_TCW_2 (0x4UL << ETH_DMAC0TXCR_TCW_Pos) /*…