DdrHoldHalfCycle (reference) in projects: hal_stm32-latest

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Searched refs:DdrHoldHalfCycle (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
D	stm32h7xx_hal_qspi.c	812 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 901 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1523 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1623 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1727 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2532 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2548 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2564 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2579 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2600 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
D	stm32f4xx_hal_qspi.c	809 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 897 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1670 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1769 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1873 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2781 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2797 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2813 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2828 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2849 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
D	stm32f7xx_hal_qspi.c	813 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 901 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1595 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1694 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1798 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2706 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2722 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2735 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2750 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2768 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
D	stm32mp1xx_hal_qspi.c	831 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 920 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1542 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1642 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1746 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2593 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2609 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2622 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2637 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2655 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
D	stm32l4xx_hal_qspi.c	820 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 909 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1603 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1703 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1807 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2688 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2704 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2720 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2735 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2756 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
D	stm32g4xx_hal_qspi.c	804 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command() 893 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT() 1579 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling() 1679 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT() 1783 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped() 2662 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2678 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2694 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2709 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() 2730 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \| in QSPI_Config() [all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_hal_qspi.h	`159 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
D	stm32f7xx_hal_qspi.h	`158 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_hal_qspi.h	`159 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
D	stm32f4xx_hal_qspi.h	`158 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_hal_qspi.h	`160 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
D	stm32g4xx_hal_qspi.h	`158 …uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the d… member`

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