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Searched refs:DTS_CFGR1_REFCLK_SEL_Msk (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h6618 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
6619 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h523xx.h9057 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
9058 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h562xx.h9783 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
9784 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h533xx.h9466 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
9467 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h573xx.h12276 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
12277 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h563xx.h11867 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
11868 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h17521 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
17522 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7b0xx.h18001 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
18002 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7b0xxq.h18013 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
18014 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7a3xxq.h17533 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
17534 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7b3xx.h18008 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
18009 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7b3xxq.h18020 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
18021 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h730xxq.h19701 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19702 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h733xx.h19689 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19690 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h725xx.h19214 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19215 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h730xx.h19689 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19690 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h735xx.h19701 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19702 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h723xx.h19202 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
19203 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5480 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
5481 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7s7xx.h6004 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
6005 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7s3xx.h5925 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
5926 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32h7r7xx.h5557 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
5558 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h31904 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
31905 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32mp151fxx_cm4.h32067 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
32068 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…
Dstm32mp151axx_ca7.h31904 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ macro
31905 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selecti…

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