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Searched refs:DMA_SxCR_TCIE (Results 1 – 25 of 97) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h2578 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_EnableIT_TC()
2678 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_DisableIT_TC()
2778 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); in LL_DMA_IsEnabledIT_TC()
Dstm32f2xx_hal_dma.h339 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h2611 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_EnableIT_TC()
2711 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_DisableIT_TC()
2811 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); in LL_DMA_IsEnabledIT_TC()
Dstm32f7xx_hal_dma.h323 #define DMA_IT_TC DMA_SxCR_TCIE
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h2588 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_EnableIT_TC()
2688 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); in LL_DMA_DisableIT_TC()
2788 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); in LL_DMA_IsEnabledIT_TC()
Dstm32f4xx_hal_dma.h349 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h2875 …ET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); in LL_DMA_EnableIT_TC()
2985 …AR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); in LL_DMA_DisableIT_TC()
3095 …eDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1U… in LL_DMA_IsEnabledIT_TC()
Dstm32mp1xx_hal_dma.h507 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h3018 …ET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); in LL_DMA_EnableIT_TC()
3128 …AR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); in LL_DMA_DisableIT_TC()
3238 …eDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1U… in LL_DMA_IsEnabledIT_TC()
Dstm32h7xx_hal_dma.h585 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1537 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f410rx.h1537 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f410tx.h1527 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f401xc.h1478 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f401xe.h1478 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f411xe.h1481 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f405xx.h5570 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f412cx.h5631 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f415xx.h5752 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f423xx.h6024 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5722 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f205xx.h5572 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f207xx.h5871 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5542 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro
Dstm32f722xx.h5526 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk macro

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