Searched refs:DMA_SxCR_MINC_Pos (Results 1 – 25 of 87) sorted by relevance
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1518 #define DMA_SxCR_MINC_Pos (10U) macro1519 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
1508 #define DMA_SxCR_MINC_Pos (10U) macro1509 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
1459 #define DMA_SxCR_MINC_Pos (10U) macro1460 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
1462 #define DMA_SxCR_MINC_Pos (10U) macro1463 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5551 #define DMA_SxCR_MINC_Pos (10U) macro5552 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5612 #define DMA_SxCR_MINC_Pos (10U) macro5613 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5733 #define DMA_SxCR_MINC_Pos (10U) macro5734 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6005 #define DMA_SxCR_MINC_Pos (10U) macro6006 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5851 #define DMA_SxCR_MINC_Pos (10U) macro5852 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5672 #define DMA_SxCR_MINC_Pos (10U) macro5673 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5666 #define DMA_SxCR_MINC_Pos (10U) macro5667 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5668 #define DMA_SxCR_MINC_Pos (10U) macro5669 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5969 #define DMA_SxCR_MINC_Pos (10U) macro5970 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5942 #define DMA_SxCR_MINC_Pos (10U) macro5943 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5703 #define DMA_SxCR_MINC_Pos (10U) macro5704 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5553 #define DMA_SxCR_MINC_Pos (10U) macro5554 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5852 #define DMA_SxCR_MINC_Pos (10U) macro5853 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6002 #define DMA_SxCR_MINC_Pos (10U) macro6003 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5523 #define DMA_SxCR_MINC_Pos (10U) macro5524 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5507 #define DMA_SxCR_MINC_Pos (10U) macro5508 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5737 #define DMA_SxCR_MINC_Pos (10U) macro5738 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5721 #define DMA_SxCR_MINC_Pos (10U) macro5722 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
