Home
last modified time | relevance | path

Searched refs:DMA_SxCR_HTIE (Results 1 – 25 of 97) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h2538 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_EnableIT_HT()
2638 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_DisableIT_HT()
2738 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); in LL_DMA_IsEnabledIT_HT()
Dstm32f2xx_hal_dma.h340 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h2571 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_EnableIT_HT()
2671 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_DisableIT_HT()
2771 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); in LL_DMA_IsEnabledIT_HT()
Dstm32f7xx_hal_dma.h324 #define DMA_IT_HT DMA_SxCR_HTIE
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h2548 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_EnableIT_HT()
2648 …DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); in LL_DMA_DisableIT_HT()
2748 …f*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); in LL_DMA_IsEnabledIT_HT()
Dstm32f4xx_hal_dma.h350 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h2831 …ET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); in LL_DMA_EnableIT_HT()
2941 …AR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); in LL_DMA_DisableIT_HT()
3051 …eDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1U… in LL_DMA_IsEnabledIT_HT()
Dstm32mp1xx_hal_dma.h508 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h2974 …ET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); in LL_DMA_EnableIT_HT()
3084 …AR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); in LL_DMA_DisableIT_HT()
3194 …eDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1U… in LL_DMA_IsEnabledIT_HT()
Dstm32h7xx_hal_dma.h586 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1540 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f410rx.h1540 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f410tx.h1530 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f401xc.h1481 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f401xe.h1481 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f411xe.h1484 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f405xx.h5573 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f412cx.h5634 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f415xx.h5755 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f423xx.h6027 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5725 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f205xx.h5575 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f207xx.h5874 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5545 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro
Dstm32f722xx.h5529 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk macro

1234