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Searched refs:DMA_SxCR_EN (Results 1 – 25 of 102) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_dma.c222 while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_Init()
665 while (((*enableRegister) & DMA_SxCR_EN) != 0U) in HAL_DMA_Abort()
1111 while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); in HAL_DMA_IRQHandler()
1113 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_dma.c215 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
944 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_dma.c214 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
946 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dma.c212 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
544 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
940 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h486 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_EnableStream()
506 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_DisableStream()
526 …Def*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); in LL_DMA_IsEnabledStream()
Dstm32f2xx_hal_dma.h407 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
414 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h499 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_EnableStream()
519 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_DisableStream()
539 …Def*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); in LL_DMA_IsEnabledStream()
Dstm32f7xx_hal_dma.h391 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
398 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_dma.c262 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_Init()
835 while(((*enableRegister) & DMA_SxCR_EN) != 0U) in HAL_DMA_Abort()
1407 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); in HAL_DMA_IRQHandler()
1409 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h496 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_EnableStream()
516 …((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); in LL_DMA_DisableStream()
536 …Def*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); in LL_DMA_IsEnabledStream()
Dstm32f4xx_hal_dma.h417 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
424 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h478 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); in LL_DMA_EnableStream()
500 …LEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); in LL_DMA_DisableStream()
522 …peDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL… in LL_DMA_IsEnabledStream()
Dstm32mp1xx_hal_dma.h579 …e __HAL_DMA_ENABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN)
586 …__HAL_DMA_DISABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h493 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); in LL_DMA_EnableStream()
515 …LEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); in LL_DMA_DisableStream()
537 …peDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL… in LL_DMA_IsEnabledStream()
Dstm32h7xx_hal_dma.h698 …((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
707 …(__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1549 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f410rx.h1549 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f410tx.h1539 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f401xc.h1490 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f401xe.h1490 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f411xe.h1493 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f405xx.h5582 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f412cx.h5643 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5734 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro
Dstm32f205xx.h5584 #define DMA_SxCR_EN DMA_SxCR_EN_Msk macro

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