Home
last modified time | relevance | path

Searched refs:DMA_SxCR_CHSEL_Pos (Results 1 – 25 of 41) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5482 #define DMA_SxCR_CHSEL_Pos (25U) macro
5483 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5485 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5486 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5487 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5488 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f722xx.h5466 #define DMA_SxCR_CHSEL_Pos (25U) macro
5467 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5469 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5470 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5471 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5472 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f730xx.h5696 #define DMA_SxCR_CHSEL_Pos (25U) macro
5697 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5699 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5700 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5701 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5702 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f733xx.h5696 #define DMA_SxCR_CHSEL_Pos (25U) macro
5697 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5699 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5700 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5701 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5702 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f732xx.h5680 #define DMA_SxCR_CHSEL_Pos (25U) macro
5681 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5683 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5684 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5685 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5686 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f765xx.h6455 #define DMA_SxCR_CHSEL_Pos (25U) macro
6456 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6458 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6459 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6460 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6461 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f777xx.h6737 #define DMA_SxCR_CHSEL_Pos (25U) macro
6738 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6740 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6741 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6742 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6743 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f767xx.h6549 #define DMA_SxCR_CHSEL_Pos (25U) macro
6550 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6552 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6553 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6554 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6555 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f750xx.h6243 #define DMA_SxCR_CHSEL_Pos (25U) macro
6244 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6246 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6247 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6248 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f745xx.h6000 #define DMA_SxCR_CHSEL_Pos (25U) macro
6001 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6003 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6004 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6005 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f756xx.h6243 #define DMA_SxCR_CHSEL_Pos (25U) macro
6244 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6246 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6247 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6248 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f746xx.h6055 #define DMA_SxCR_CHSEL_Pos (25U) macro
6056 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6058 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6059 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6060 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f779xx.h6820 #define DMA_SxCR_CHSEL_Pos (25U) macro
6821 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6823 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6824 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6825 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6826 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
Dstm32f769xx.h6632 #define DMA_SxCR_CHSEL_Pos (25U) macro
6633 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6635 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6636 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6637 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6638 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5663 #define DMA_SxCR_CHSEL_Pos (25U) macro
5664 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5666 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5667 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5668 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f205xx.h5513 #define DMA_SxCR_CHSEL_Pos (25U) macro
5514 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5516 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5517 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5518 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f207xx.h5812 #define DMA_SxCR_CHSEL_Pos (25U) macro
5813 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5815 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5816 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5817 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
Dstm32f217xx.h5962 #define DMA_SxCR_CHSEL_Pos (25U) macro
5963 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5965 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5966 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5967 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1478 #define DMA_SxCR_CHSEL_Pos (25U) macro
1479 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f410rx.h1478 #define DMA_SxCR_CHSEL_Pos (25U) macro
1479 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f410tx.h1468 #define DMA_SxCR_CHSEL_Pos (25U) macro
1469 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f401xc.h1419 #define DMA_SxCR_CHSEL_Pos (25U) macro
1420 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f401xe.h1419 #define DMA_SxCR_CHSEL_Pos (25U) macro
1420 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f411xe.h1422 #define DMA_SxCR_CHSEL_Pos (25U) macro
1423 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
Dstm32f405xx.h5511 #define DMA_SxCR_CHSEL_Pos (25U) macro
5512 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */

12