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Searched refs:DMA_SxCR_ACK_Pos (Results 1 – 25 of 51) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1552 #define DMA_SxCR_ACK_Pos (20U) macro
1553 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f410rx.h1552 #define DMA_SxCR_ACK_Pos (20U) macro
1553 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f410tx.h1542 #define DMA_SxCR_ACK_Pos (20U) macro
1543 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f401xc.h1493 #define DMA_SxCR_ACK_Pos (20U) macro
1494 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f401xe.h1493 #define DMA_SxCR_ACK_Pos (20U) macro
1494 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f411xe.h1496 #define DMA_SxCR_ACK_Pos (20U) macro
1497 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f405xx.h5585 #define DMA_SxCR_ACK_Pos (20U) macro
5586 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f412cx.h5646 #define DMA_SxCR_ACK_Pos (20U) macro
5647 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f415xx.h5767 #define DMA_SxCR_ACK_Pos (20U) macro
5768 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f423xx.h6039 #define DMA_SxCR_ACK_Pos (20U) macro
6040 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f407xx.h5885 #define DMA_SxCR_ACK_Pos (20U) macro
5886 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f412zx.h5706 #define DMA_SxCR_ACK_Pos (20U) macro
5707 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f412rx.h5700 #define DMA_SxCR_ACK_Pos (20U) macro
5701 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f412vx.h5702 #define DMA_SxCR_ACK_Pos (20U) macro
5703 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f413xx.h6003 #define DMA_SxCR_ACK_Pos (20U) macro
6004 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f427xx.h5976 #define DMA_SxCR_ACK_Pos (20U) macro
5977 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f446xx.h6053 #define DMA_SxCR_ACK_Pos (20U) macro
6054 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f417xx.h6064 #define DMA_SxCR_ACK_Pos (20U) macro
6065 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f429xx.h6035 #define DMA_SxCR_ACK_Pos (20U) macro
6036 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f439xx.h6222 #define DMA_SxCR_ACK_Pos (20U) macro
6223 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f437xx.h6168 #define DMA_SxCR_ACK_Pos (20U) macro
6169 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5737 #define DMA_SxCR_ACK_Pos (20U) macro
5738 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f205xx.h5587 #define DMA_SxCR_ACK_Pos (20U) macro
5588 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f207xx.h5886 #define DMA_SxCR_ACK_Pos (20U) macro
5887 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
Dstm32f217xx.h6036 #define DMA_SxCR_ACK_Pos (20U) macro
6037 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */

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