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Searched refs:DMA_LISR_TEIF0_Pos (Results 1 – 25 of 87) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1648 #define DMA_LISR_TEIF0_Pos (3U) macro
1649 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f410rx.h1648 #define DMA_LISR_TEIF0_Pos (3U) macro
1649 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f410tx.h1638 #define DMA_LISR_TEIF0_Pos (3U) macro
1639 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f401xc.h1589 #define DMA_LISR_TEIF0_Pos (3U) macro
1590 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f401xe.h1589 #define DMA_LISR_TEIF0_Pos (3U) macro
1590 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f411xe.h1592 #define DMA_LISR_TEIF0_Pos (3U) macro
1593 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f405xx.h5681 #define DMA_LISR_TEIF0_Pos (3U) macro
5682 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f412cx.h5742 #define DMA_LISR_TEIF0_Pos (3U) macro
5743 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f415xx.h5863 #define DMA_LISR_TEIF0_Pos (3U) macro
5864 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f423xx.h6135 #define DMA_LISR_TEIF0_Pos (3U) macro
6136 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f407xx.h5981 #define DMA_LISR_TEIF0_Pos (3U) macro
5982 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f412zx.h5802 #define DMA_LISR_TEIF0_Pos (3U) macro
5803 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f412rx.h5796 #define DMA_LISR_TEIF0_Pos (3U) macro
5797 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f412vx.h5798 #define DMA_LISR_TEIF0_Pos (3U) macro
5799 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f413xx.h6099 #define DMA_LISR_TEIF0_Pos (3U) macro
6100 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f427xx.h6072 #define DMA_LISR_TEIF0_Pos (3U) macro
6073 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5833 #define DMA_LISR_TEIF0_Pos (3U) macro
5834 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f205xx.h5683 #define DMA_LISR_TEIF0_Pos (3U) macro
5684 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f207xx.h5982 #define DMA_LISR_TEIF0_Pos (3U) macro
5983 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f217xx.h6132 #define DMA_LISR_TEIF0_Pos (3U) macro
6133 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5648 #define DMA_LISR_TEIF0_Pos (3U) macro
5649 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f722xx.h5632 #define DMA_LISR_TEIF0_Pos (3U) macro
5633 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f730xx.h5862 #define DMA_LISR_TEIF0_Pos (3U) macro
5863 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f733xx.h5862 #define DMA_LISR_TEIF0_Pos (3U) macro
5863 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
Dstm32f732xx.h5846 #define DMA_LISR_TEIF0_Pos (3U) macro
5847 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */

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