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Searched refs:DMA_LISR_FEIF1_Pos (Results 1 – 25 of 87) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1639 #define DMA_LISR_FEIF1_Pos (6U) macro
1640 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f410rx.h1639 #define DMA_LISR_FEIF1_Pos (6U) macro
1640 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f410tx.h1629 #define DMA_LISR_FEIF1_Pos (6U) macro
1630 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f401xc.h1580 #define DMA_LISR_FEIF1_Pos (6U) macro
1581 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f401xe.h1580 #define DMA_LISR_FEIF1_Pos (6U) macro
1581 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f411xe.h1583 #define DMA_LISR_FEIF1_Pos (6U) macro
1584 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f405xx.h5672 #define DMA_LISR_FEIF1_Pos (6U) macro
5673 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f412cx.h5733 #define DMA_LISR_FEIF1_Pos (6U) macro
5734 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f415xx.h5854 #define DMA_LISR_FEIF1_Pos (6U) macro
5855 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f423xx.h6126 #define DMA_LISR_FEIF1_Pos (6U) macro
6127 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f407xx.h5972 #define DMA_LISR_FEIF1_Pos (6U) macro
5973 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f412zx.h5793 #define DMA_LISR_FEIF1_Pos (6U) macro
5794 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f412rx.h5787 #define DMA_LISR_FEIF1_Pos (6U) macro
5788 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f412vx.h5789 #define DMA_LISR_FEIF1_Pos (6U) macro
5790 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f413xx.h6090 #define DMA_LISR_FEIF1_Pos (6U) macro
6091 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f427xx.h6063 #define DMA_LISR_FEIF1_Pos (6U) macro
6064 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5824 #define DMA_LISR_FEIF1_Pos (6U) macro
5825 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f205xx.h5674 #define DMA_LISR_FEIF1_Pos (6U) macro
5675 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f207xx.h5973 #define DMA_LISR_FEIF1_Pos (6U) macro
5974 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f217xx.h6123 #define DMA_LISR_FEIF1_Pos (6U) macro
6124 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5639 #define DMA_LISR_FEIF1_Pos (6U) macro
5640 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f722xx.h5623 #define DMA_LISR_FEIF1_Pos (6U) macro
5624 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f730xx.h5853 #define DMA_LISR_FEIF1_Pos (6U) macro
5854 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f733xx.h5853 #define DMA_LISR_FEIF1_Pos (6U) macro
5854 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
Dstm32f732xx.h5837 #define DMA_LISR_FEIF1_Pos (6U) macro
5838 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */

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