Searched refs:DMA_LIFCR_CHTIF0_Pos (Results 1 – 25 of 87) sorted by relevance
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1769 #define DMA_LIFCR_CHTIF0_Pos (4U) macro1770 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
1759 #define DMA_LIFCR_CHTIF0_Pos (4U) macro1760 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
1710 #define DMA_LIFCR_CHTIF0_Pos (4U) macro1711 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
1713 #define DMA_LIFCR_CHTIF0_Pos (4U) macro1714 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5802 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5803 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5863 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5864 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5984 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5985 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6256 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6257 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6102 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6103 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5923 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5924 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5917 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5918 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5919 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5920 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6220 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6221 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6193 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6194 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5954 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5955 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5804 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5805 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6103 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6104 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6253 #define DMA_LIFCR_CHTIF0_Pos (4U) macro6254 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5769 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5770 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5753 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5754 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5983 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5984 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5967 #define DMA_LIFCR_CHTIF0_Pos (4U) macro5968 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
