Home
last modified time | relevance | path

Searched refs:DMA_LIFCR_CFEIF0_Pos (Results 1 – 25 of 87) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1778 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1779 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f410rx.h1778 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1779 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f410tx.h1768 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1769 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f401xc.h1719 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1720 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f401xe.h1719 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1720 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f411xe.h1722 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
1723 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f405xx.h5811 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5812 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f412cx.h5872 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5873 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f415xx.h5993 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5994 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f423xx.h6265 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6266 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f407xx.h6111 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6112 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f412zx.h5932 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5933 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f412rx.h5926 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5927 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f412vx.h5928 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5929 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f413xx.h6229 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6230 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f427xx.h6202 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6203 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5963 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5964 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f205xx.h5813 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5814 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f207xx.h6112 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6113 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f217xx.h6262 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
6263 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5778 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5779 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f722xx.h5762 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5763 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f730xx.h5992 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5993 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f733xx.h5992 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5993 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
Dstm32f732xx.h5976 #define DMA_LIFCR_CFEIF0_Pos (0U) macro
5977 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */

1234