Home
last modified time | relevance | path

Searched refs:DMA_IFCR_CTEIF5_Pos (Results 1 – 25 of 158) sorted by relevance

1234567

/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h2974 #define DMA_IFCR_CTEIF5_Pos (19U) macro
2975 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f101xb.h3036 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3037 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f100xb.h3188 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3189 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f102x6.h3023 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3024 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f100xe.h3535 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3536 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f101xg.h3507 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3508 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f101xe.h3431 #define DMA_IFCR_CTEIF5_Pos (19U) macro
3432 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h1079 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1080 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f030x8.h1101 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1102 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f070x6.h1124 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1125 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f031x6.h1095 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1096 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f030xc.h1120 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1121 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f038xx.h1094 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1095 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32f070xb.h1156 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1157 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h1361 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1362 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l010x8.h1124 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1125 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l010xb.h1132 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1133 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l011xx.h1197 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1198 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l021xx.h1325 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1326 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l031xx.h1233 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1234 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l051xx.h1274 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1275 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l010x4.h1116 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1117 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l010x6.h1122 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1123 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l081xx.h1433 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1434 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Dstm32l071xx.h1305 #define DMA_IFCR_CTEIF5_Pos (19U) macro
1306 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */

1234567