Searched refs:DMA_IFCR_CTCIF2_Pos (Results 1 – 25 of 160) sorted by relevance
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2932 #define DMA_IFCR_CTCIF2_Pos (5U) macro2933 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
2994 #define DMA_IFCR_CTCIF2_Pos (5U) macro2995 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3146 #define DMA_IFCR_CTCIF2_Pos (5U) macro3147 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
2981 #define DMA_IFCR_CTCIF2_Pos (5U) macro2982 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3493 #define DMA_IFCR_CTCIF2_Pos (5U) macro3494 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3465 #define DMA_IFCR_CTCIF2_Pos (5U) macro3466 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3389 #define DMA_IFCR_CTCIF2_Pos (5U) macro3390 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1037 #define DMA_IFCR_CTCIF2_Pos (5U) macro1038 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1059 #define DMA_IFCR_CTCIF2_Pos (5U) macro1060 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1082 #define DMA_IFCR_CTCIF2_Pos (5U) macro1083 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1053 #define DMA_IFCR_CTCIF2_Pos (5U) macro1054 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1078 #define DMA_IFCR_CTCIF2_Pos (5U) macro1079 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1052 #define DMA_IFCR_CTCIF2_Pos (5U) macro1053 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1114 #define DMA_IFCR_CTCIF2_Pos (5U) macro1115 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1319 #define DMA_IFCR_CTCIF2_Pos (5U) macro1320 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1090 #define DMA_IFCR_CTCIF2_Pos (5U) macro1091 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1155 #define DMA_IFCR_CTCIF2_Pos (5U) macro1156 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1283 #define DMA_IFCR_CTCIF2_Pos (5U) macro1284 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1191 #define DMA_IFCR_CTCIF2_Pos (5U) macro1192 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1232 #define DMA_IFCR_CTCIF2_Pos (5U) macro1233 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1074 #define DMA_IFCR_CTCIF2_Pos (5U) macro1075 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1080 #define DMA_IFCR_CTCIF2_Pos (5U) macro1081 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1391 #define DMA_IFCR_CTCIF2_Pos (5U) macro1392 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1263 #define DMA_IFCR_CTCIF2_Pos (5U) macro1264 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
