Searched refs:DMA_IFCR_CTCIF1_Pos (Results 1 – 25 of 160) sorted by relevance
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2920 #define DMA_IFCR_CTCIF1_Pos (1U) macro2921 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
2982 #define DMA_IFCR_CTCIF1_Pos (1U) macro2983 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3134 #define DMA_IFCR_CTCIF1_Pos (1U) macro3135 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
2969 #define DMA_IFCR_CTCIF1_Pos (1U) macro2970 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3481 #define DMA_IFCR_CTCIF1_Pos (1U) macro3482 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3453 #define DMA_IFCR_CTCIF1_Pos (1U) macro3454 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3377 #define DMA_IFCR_CTCIF1_Pos (1U) macro3378 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1025 #define DMA_IFCR_CTCIF1_Pos (1U) macro1026 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1047 #define DMA_IFCR_CTCIF1_Pos (1U) macro1048 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1070 #define DMA_IFCR_CTCIF1_Pos (1U) macro1071 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1041 #define DMA_IFCR_CTCIF1_Pos (1U) macro1042 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1066 #define DMA_IFCR_CTCIF1_Pos (1U) macro1067 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1040 #define DMA_IFCR_CTCIF1_Pos (1U) macro1041 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1102 #define DMA_IFCR_CTCIF1_Pos (1U) macro1103 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1307 #define DMA_IFCR_CTCIF1_Pos (1U) macro1308 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1078 #define DMA_IFCR_CTCIF1_Pos (1U) macro1079 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1143 #define DMA_IFCR_CTCIF1_Pos (1U) macro1144 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1271 #define DMA_IFCR_CTCIF1_Pos (1U) macro1272 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1179 #define DMA_IFCR_CTCIF1_Pos (1U) macro1180 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1220 #define DMA_IFCR_CTCIF1_Pos (1U) macro1221 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1062 #define DMA_IFCR_CTCIF1_Pos (1U) macro1063 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1068 #define DMA_IFCR_CTCIF1_Pos (1U) macro1069 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1379 #define DMA_IFCR_CTCIF1_Pos (1U) macro1380 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1251 #define DMA_IFCR_CTCIF1_Pos (1U) macro1252 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
