Searched refs:DMA_IFCR_CHTIF2_Pos (Results 1 – 25 of 160) sorted by relevance
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2935 #define DMA_IFCR_CHTIF2_Pos (6U) macro2936 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
2997 #define DMA_IFCR_CHTIF2_Pos (6U) macro2998 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3149 #define DMA_IFCR_CHTIF2_Pos (6U) macro3150 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
2984 #define DMA_IFCR_CHTIF2_Pos (6U) macro2985 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3496 #define DMA_IFCR_CHTIF2_Pos (6U) macro3497 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3468 #define DMA_IFCR_CHTIF2_Pos (6U) macro3469 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3392 #define DMA_IFCR_CHTIF2_Pos (6U) macro3393 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1040 #define DMA_IFCR_CHTIF2_Pos (6U) macro1041 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1062 #define DMA_IFCR_CHTIF2_Pos (6U) macro1063 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1085 #define DMA_IFCR_CHTIF2_Pos (6U) macro1086 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1056 #define DMA_IFCR_CHTIF2_Pos (6U) macro1057 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1081 #define DMA_IFCR_CHTIF2_Pos (6U) macro1082 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1055 #define DMA_IFCR_CHTIF2_Pos (6U) macro1056 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1117 #define DMA_IFCR_CHTIF2_Pos (6U) macro1118 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1322 #define DMA_IFCR_CHTIF2_Pos (6U) macro1323 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1093 #define DMA_IFCR_CHTIF2_Pos (6U) macro1094 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1158 #define DMA_IFCR_CHTIF2_Pos (6U) macro1159 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1286 #define DMA_IFCR_CHTIF2_Pos (6U) macro1287 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1194 #define DMA_IFCR_CHTIF2_Pos (6U) macro1195 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1235 #define DMA_IFCR_CHTIF2_Pos (6U) macro1236 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1077 #define DMA_IFCR_CHTIF2_Pos (6U) macro1078 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1083 #define DMA_IFCR_CHTIF2_Pos (6U) macro1084 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1394 #define DMA_IFCR_CHTIF2_Pos (6U) macro1395 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1266 #define DMA_IFCR_CHTIF2_Pos (6U) macro1267 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
