Searched refs:DMA_HISR_TEIF5_Pos (Results 1 – 25 of 87) sorted by relevance
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1695 #define DMA_HISR_TEIF5_Pos (9U) macro1696 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
1685 #define DMA_HISR_TEIF5_Pos (9U) macro1686 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
1636 #define DMA_HISR_TEIF5_Pos (9U) macro1637 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
1639 #define DMA_HISR_TEIF5_Pos (9U) macro1640 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5728 #define DMA_HISR_TEIF5_Pos (9U) macro5729 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5789 #define DMA_HISR_TEIF5_Pos (9U) macro5790 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5910 #define DMA_HISR_TEIF5_Pos (9U) macro5911 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6182 #define DMA_HISR_TEIF5_Pos (9U) macro6183 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6028 #define DMA_HISR_TEIF5_Pos (9U) macro6029 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5849 #define DMA_HISR_TEIF5_Pos (9U) macro5850 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5843 #define DMA_HISR_TEIF5_Pos (9U) macro5844 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5845 #define DMA_HISR_TEIF5_Pos (9U) macro5846 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6146 #define DMA_HISR_TEIF5_Pos (9U) macro6147 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6119 #define DMA_HISR_TEIF5_Pos (9U) macro6120 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5880 #define DMA_HISR_TEIF5_Pos (9U) macro5881 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5730 #define DMA_HISR_TEIF5_Pos (9U) macro5731 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6029 #define DMA_HISR_TEIF5_Pos (9U) macro6030 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6179 #define DMA_HISR_TEIF5_Pos (9U) macro6180 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5695 #define DMA_HISR_TEIF5_Pos (9U) macro5696 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5679 #define DMA_HISR_TEIF5_Pos (9U) macro5680 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5909 #define DMA_HISR_TEIF5_Pos (9U) macro5910 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5893 #define DMA_HISR_TEIF5_Pos (9U) macro5894 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
