Searched refs:DMA_HISR_TEIF4_Pos (Results 1 – 25 of 87) sorted by relevance
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1710 #define DMA_HISR_TEIF4_Pos (3U) macro1711 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
1700 #define DMA_HISR_TEIF4_Pos (3U) macro1701 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
1651 #define DMA_HISR_TEIF4_Pos (3U) macro1652 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
1654 #define DMA_HISR_TEIF4_Pos (3U) macro1655 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5743 #define DMA_HISR_TEIF4_Pos (3U) macro5744 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5804 #define DMA_HISR_TEIF4_Pos (3U) macro5805 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5925 #define DMA_HISR_TEIF4_Pos (3U) macro5926 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6197 #define DMA_HISR_TEIF4_Pos (3U) macro6198 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6043 #define DMA_HISR_TEIF4_Pos (3U) macro6044 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5864 #define DMA_HISR_TEIF4_Pos (3U) macro5865 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5858 #define DMA_HISR_TEIF4_Pos (3U) macro5859 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5860 #define DMA_HISR_TEIF4_Pos (3U) macro5861 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6161 #define DMA_HISR_TEIF4_Pos (3U) macro6162 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6134 #define DMA_HISR_TEIF4_Pos (3U) macro6135 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5895 #define DMA_HISR_TEIF4_Pos (3U) macro5896 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5745 #define DMA_HISR_TEIF4_Pos (3U) macro5746 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6044 #define DMA_HISR_TEIF4_Pos (3U) macro6045 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6194 #define DMA_HISR_TEIF4_Pos (3U) macro6195 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5710 #define DMA_HISR_TEIF4_Pos (3U) macro5711 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5694 #define DMA_HISR_TEIF4_Pos (3U) macro5695 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5924 #define DMA_HISR_TEIF4_Pos (3U) macro5925 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5908 #define DMA_HISR_TEIF4_Pos (3U) macro5909 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
