Searched refs:DMA_HISR_TCIF5_Pos (Results 1 – 25 of 87) sorted by relevance
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1689 #define DMA_HISR_TCIF5_Pos (11U) macro1690 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
1679 #define DMA_HISR_TCIF5_Pos (11U) macro1680 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
1630 #define DMA_HISR_TCIF5_Pos (11U) macro1631 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
1633 #define DMA_HISR_TCIF5_Pos (11U) macro1634 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5722 #define DMA_HISR_TCIF5_Pos (11U) macro5723 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5783 #define DMA_HISR_TCIF5_Pos (11U) macro5784 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5904 #define DMA_HISR_TCIF5_Pos (11U) macro5905 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6176 #define DMA_HISR_TCIF5_Pos (11U) macro6177 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6022 #define DMA_HISR_TCIF5_Pos (11U) macro6023 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5843 #define DMA_HISR_TCIF5_Pos (11U) macro5844 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5837 #define DMA_HISR_TCIF5_Pos (11U) macro5838 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5839 #define DMA_HISR_TCIF5_Pos (11U) macro5840 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6140 #define DMA_HISR_TCIF5_Pos (11U) macro6141 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6113 #define DMA_HISR_TCIF5_Pos (11U) macro6114 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5874 #define DMA_HISR_TCIF5_Pos (11U) macro5875 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5724 #define DMA_HISR_TCIF5_Pos (11U) macro5725 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6023 #define DMA_HISR_TCIF5_Pos (11U) macro6024 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6173 #define DMA_HISR_TCIF5_Pos (11U) macro6174 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5689 #define DMA_HISR_TCIF5_Pos (11U) macro5690 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5673 #define DMA_HISR_TCIF5_Pos (11U) macro5674 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5903 #define DMA_HISR_TCIF5_Pos (11U) macro5904 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5887 #define DMA_HISR_TCIF5_Pos (11U) macro5888 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
