Home
last modified time | relevance | path

Searched refs:DMA_HISR_TCIF5_Msk (Results 1 – 25 of 87) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1690 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1691 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f410rx.h1690 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1691 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f410tx.h1680 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1681 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f401xc.h1631 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1632 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f401xe.h1631 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1632 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f411xe.h1634 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
1635 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f405xx.h5723 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5724 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f412cx.h5784 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5785 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f415xx.h5905 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5906 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f423xx.h6177 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6178 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f407xx.h6023 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6024 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f412zx.h5844 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5845 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f412rx.h5838 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5839 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f412vx.h5840 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5841 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f413xx.h6141 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6142 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f427xx.h6114 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6115 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h5875 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5876 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f205xx.h5725 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5726 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f207xx.h6024 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6025 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f217xx.h6174 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
6175 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5690 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5691 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f722xx.h5674 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5675 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f730xx.h5904 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5905 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f733xx.h5904 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5905 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
Dstm32f732xx.h5888 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ macro
5889 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk

1234