Searched refs:DMA_HISR_HTIF5_Pos (Results 1 – 25 of 87) sorted by relevance
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1692 #define DMA_HISR_HTIF5_Pos (10U) macro1693 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
1682 #define DMA_HISR_HTIF5_Pos (10U) macro1683 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
1633 #define DMA_HISR_HTIF5_Pos (10U) macro1634 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
1636 #define DMA_HISR_HTIF5_Pos (10U) macro1637 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5725 #define DMA_HISR_HTIF5_Pos (10U) macro5726 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5786 #define DMA_HISR_HTIF5_Pos (10U) macro5787 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5907 #define DMA_HISR_HTIF5_Pos (10U) macro5908 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6179 #define DMA_HISR_HTIF5_Pos (10U) macro6180 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6025 #define DMA_HISR_HTIF5_Pos (10U) macro6026 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5846 #define DMA_HISR_HTIF5_Pos (10U) macro5847 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5840 #define DMA_HISR_HTIF5_Pos (10U) macro5841 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5842 #define DMA_HISR_HTIF5_Pos (10U) macro5843 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6143 #define DMA_HISR_HTIF5_Pos (10U) macro6144 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6116 #define DMA_HISR_HTIF5_Pos (10U) macro6117 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5877 #define DMA_HISR_HTIF5_Pos (10U) macro5878 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5727 #define DMA_HISR_HTIF5_Pos (10U) macro5728 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6026 #define DMA_HISR_HTIF5_Pos (10U) macro6027 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6176 #define DMA_HISR_HTIF5_Pos (10U) macro6177 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5692 #define DMA_HISR_HTIF5_Pos (10U) macro5693 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5676 #define DMA_HISR_HTIF5_Pos (10U) macro5677 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5906 #define DMA_HISR_HTIF5_Pos (10U) macro5907 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5890 #define DMA_HISR_HTIF5_Pos (10U) macro5891 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
