Searched refs:DMA_HISR_FEIF5_Pos (Results 1 – 25 of 87) sorted by relevance
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1701 #define DMA_HISR_FEIF5_Pos (6U) macro1702 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
1691 #define DMA_HISR_FEIF5_Pos (6U) macro1692 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
1642 #define DMA_HISR_FEIF5_Pos (6U) macro1643 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
1645 #define DMA_HISR_FEIF5_Pos (6U) macro1646 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5734 #define DMA_HISR_FEIF5_Pos (6U) macro5735 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5795 #define DMA_HISR_FEIF5_Pos (6U) macro5796 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5916 #define DMA_HISR_FEIF5_Pos (6U) macro5917 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6188 #define DMA_HISR_FEIF5_Pos (6U) macro6189 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6034 #define DMA_HISR_FEIF5_Pos (6U) macro6035 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5855 #define DMA_HISR_FEIF5_Pos (6U) macro5856 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5849 #define DMA_HISR_FEIF5_Pos (6U) macro5850 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5851 #define DMA_HISR_FEIF5_Pos (6U) macro5852 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6152 #define DMA_HISR_FEIF5_Pos (6U) macro6153 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6125 #define DMA_HISR_FEIF5_Pos (6U) macro6126 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5886 #define DMA_HISR_FEIF5_Pos (6U) macro5887 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5736 #define DMA_HISR_FEIF5_Pos (6U) macro5737 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6035 #define DMA_HISR_FEIF5_Pos (6U) macro6036 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6185 #define DMA_HISR_FEIF5_Pos (6U) macro6186 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5701 #define DMA_HISR_FEIF5_Pos (6U) macro5702 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5685 #define DMA_HISR_FEIF5_Pos (6U) macro5686 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5915 #define DMA_HISR_FEIF5_Pos (6U) macro5916 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5899 #define DMA_HISR_FEIF5_Pos (6U) macro5900 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
