Searched refs:DMA_HISR_FEIF4_Pos (Results 1 – 25 of 87) sorted by relevance
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1716 #define DMA_HISR_FEIF4_Pos (0U) macro1717 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
1706 #define DMA_HISR_FEIF4_Pos (0U) macro1707 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
1657 #define DMA_HISR_FEIF4_Pos (0U) macro1658 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
1660 #define DMA_HISR_FEIF4_Pos (0U) macro1661 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5749 #define DMA_HISR_FEIF4_Pos (0U) macro5750 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5810 #define DMA_HISR_FEIF4_Pos (0U) macro5811 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5931 #define DMA_HISR_FEIF4_Pos (0U) macro5932 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6203 #define DMA_HISR_FEIF4_Pos (0U) macro6204 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6049 #define DMA_HISR_FEIF4_Pos (0U) macro6050 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5870 #define DMA_HISR_FEIF4_Pos (0U) macro5871 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5864 #define DMA_HISR_FEIF4_Pos (0U) macro5865 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5866 #define DMA_HISR_FEIF4_Pos (0U) macro5867 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6167 #define DMA_HISR_FEIF4_Pos (0U) macro6168 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6140 #define DMA_HISR_FEIF4_Pos (0U) macro6141 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5901 #define DMA_HISR_FEIF4_Pos (0U) macro5902 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5751 #define DMA_HISR_FEIF4_Pos (0U) macro5752 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6050 #define DMA_HISR_FEIF4_Pos (0U) macro6051 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6200 #define DMA_HISR_FEIF4_Pos (0U) macro6201 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5716 #define DMA_HISR_FEIF4_Pos (0U) macro5717 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5700 #define DMA_HISR_FEIF4_Pos (0U) macro5701 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5930 #define DMA_HISR_FEIF4_Pos (0U) macro5931 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5914 #define DMA_HISR_FEIF4_Pos (0U) macro5915 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
