Searched refs:DMA_HISR_DMEIF5_Pos (Results 1 – 25 of 87) sorted by relevance
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1698 #define DMA_HISR_DMEIF5_Pos (8U) macro1699 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
1688 #define DMA_HISR_DMEIF5_Pos (8U) macro1689 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
1639 #define DMA_HISR_DMEIF5_Pos (8U) macro1640 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
1642 #define DMA_HISR_DMEIF5_Pos (8U) macro1643 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5731 #define DMA_HISR_DMEIF5_Pos (8U) macro5732 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5792 #define DMA_HISR_DMEIF5_Pos (8U) macro5793 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5913 #define DMA_HISR_DMEIF5_Pos (8U) macro5914 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6185 #define DMA_HISR_DMEIF5_Pos (8U) macro6186 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6031 #define DMA_HISR_DMEIF5_Pos (8U) macro6032 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5852 #define DMA_HISR_DMEIF5_Pos (8U) macro5853 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5846 #define DMA_HISR_DMEIF5_Pos (8U) macro5847 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5848 #define DMA_HISR_DMEIF5_Pos (8U) macro5849 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6149 #define DMA_HISR_DMEIF5_Pos (8U) macro6150 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6122 #define DMA_HISR_DMEIF5_Pos (8U) macro6123 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5883 #define DMA_HISR_DMEIF5_Pos (8U) macro5884 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5733 #define DMA_HISR_DMEIF5_Pos (8U) macro5734 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6032 #define DMA_HISR_DMEIF5_Pos (8U) macro6033 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6182 #define DMA_HISR_DMEIF5_Pos (8U) macro6183 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5698 #define DMA_HISR_DMEIF5_Pos (8U) macro5699 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5682 #define DMA_HISR_DMEIF5_Pos (8U) macro5683 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5912 #define DMA_HISR_DMEIF5_Pos (8U) macro5913 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5896 #define DMA_HISR_DMEIF5_Pos (8U) macro5897 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
