Home
last modified time | relevance | path

Searched refs:DMA_HIFCR_CDMEIF4_Pos (Results 1 – 25 of 87) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h1837 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1838 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f410rx.h1837 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1838 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f410tx.h1827 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1828 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f401xc.h1778 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1779 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f401xe.h1778 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1779 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f411xe.h1781 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
1782 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f405xx.h5870 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5871 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f412cx.h5931 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5932 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f415xx.h6052 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6053 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f423xx.h6324 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6325 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f407xx.h6170 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6171 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f412zx.h5991 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5992 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f412rx.h5985 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5986 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f412vx.h5987 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5988 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f413xx.h6288 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6289 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f427xx.h6261 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6262 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h6022 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6023 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f205xx.h5872 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5873 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f207xx.h6171 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6172 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f217xx.h6321 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6322 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h5837 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5838 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f722xx.h5821 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
5822 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f730xx.h6051 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6052 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f733xx.h6051 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6052 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
Dstm32f732xx.h6035 #define DMA_HIFCR_CDMEIF4_Pos (2U) macro
6036 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */

1234