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Searched refs:DMA_CTR3_SAO (Results 1 – 25 of 34) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h4474 … (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); in LL_DMA_ConfigAddrUpdateValue()
4526 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, in LL_DMA_SetSrcAddrUpdateValue()
4527 SrcAddrOffset & DMA_CTR3_SAO); in LL_DMA_SetSrcAddrUpdateValue()
4543 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h4536 … (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); in LL_DMA_ConfigAddrUpdateValue()
4594 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, in LL_DMA_SetSrcAddrUpdateValue()
4595 SrcAddrOffset & DMA_CTR3_SAO); in LL_DMA_SetSrcAddrUpdateValue()
4613 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h4356 … (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); in LL_DMA_ConfigAddrUpdateValue()
4414 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, in LL_DMA_SetSrcAddrUpdateValue()
4415 SrcAddrOffset & DMA_CTR3_SAO); in LL_DMA_SetSrcAddrUpdateValue()
4433 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h5674 … (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); in LL_DMA_ConfigAddrUpdateValue()
5732 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, in LL_DMA_SetSrcAddrUpdateValue()
5733 SrcAddrOffset & DMA_CTR3_SAO); in LL_DMA_SetSrcAddrUpdateValue()
5751 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); in LL_DMA_GetSrcAddrUpdateValue()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma_ex.c3854 pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
3859 ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
4041 offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma_ex.c3825 pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
3830 ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
3982 offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma_ex.c3852 pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
3857 ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
4040 offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma_ex.c3874 pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
3879 ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); in DMA_List_BuildNode()
4061 offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3971 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h523xx.h5333 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h562xx.h5776 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h533xx.h5742 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h573xx.h8269 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h563xx.h7860 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6421 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u535xx.h6021 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u575xx.h6420 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u585xx.h6869 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u595xx.h6676 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u5a5xx.h7125 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32u5f7xx.h6972 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5128 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h7s7xx.h5652 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h7s3xx.h5573 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro
Dstm32h7r7xx.h5205 #define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source add… macro

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