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Searched refs:DMA_CLLR_UT3 (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h940 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5030 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_EnableCTR3Update()
5046 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_DisableCTR3Update()
5062 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) in LL_DMA_IsEnabledCTR3Update()
5063 == (DMA_CLLR_UT3)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR3Update()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h951 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5240 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_EnableCTR3Update()
5258 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_DisableCTR3Update()
5276 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) in LL_DMA_IsEnabledCTR3Update()
5277 == (DMA_CLLR_UT3)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR3Update()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h934 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5060 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_EnableCTR3Update()
5078 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_DisableCTR3Update()
5096 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) in LL_DMA_IsEnabledCTR3Update()
5097 == (DMA_CLLR_UT3)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR3Update()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h987 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
5904 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
6378 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_EnableCTR3Update()
6396 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); in LL_DMA_DisableCTR3Update()
6414 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) in LL_DMA_IsEnabledCTR3Update()
6415 == (DMA_CLLR_UT3)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR3Update()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1132 …pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CL… in LL_DMA_CreateLinkNode()
1160 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4208 …lr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | in DMA_List_GetCLLRNodeInfo()
4407 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4472 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1086 …pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CL… in LL_DMA_CreateLinkNode()
1113 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4209 …lr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | in DMA_List_GetCLLRNodeInfo()
4408 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4473 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1139 …pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CL… in LL_DMA_CreateLinkNode()
1162 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …lr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | in DMA_List_GetCLLRNodeInfo()
4349 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4414 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_dma.c1203 …pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CL… in LL_DMA_CreateLinkNode()
1231 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32n6xx_hal_dma_ex.c4229 …lr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | in DMA_List_GetCLLRNodeInfo()
4428 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4493 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3996 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h523xx.h5358 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h562xx.h5801 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h533xx.h5767 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h573xx.h8294 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h563xx.h7885 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6446 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32u535xx.h6046 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32u575xx.h6445 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5153 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h7s7xx.h5677 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h7s3xx.h5598 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro
Dstm32h7r7xx.h5230 #define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update tra… macro

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