Searched refs:DMA_CCR_MINC_Pos (Results 1 – 25 of 160) sorted by relevance
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3024 #define DMA_CCR_MINC_Pos (7U) macro3025 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3086 #define DMA_CCR_MINC_Pos (7U) macro3087 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3238 #define DMA_CCR_MINC_Pos (7U) macro3239 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3073 #define DMA_CCR_MINC_Pos (7U) macro3074 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3585 #define DMA_CCR_MINC_Pos (7U) macro3586 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3557 #define DMA_CCR_MINC_Pos (7U) macro3558 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3481 #define DMA_CCR_MINC_Pos (7U) macro3482 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1105 #define DMA_CCR_MINC_Pos (7U) macro1106 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1127 #define DMA_CCR_MINC_Pos (7U) macro1128 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1150 #define DMA_CCR_MINC_Pos (7U) macro1151 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1121 #define DMA_CCR_MINC_Pos (7U) macro1122 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1146 #define DMA_CCR_MINC_Pos (7U) macro1147 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1120 #define DMA_CCR_MINC_Pos (7U) macro1121 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1182 #define DMA_CCR_MINC_Pos (7U) macro1183 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1411 #define DMA_CCR_MINC_Pos (7U) macro1412 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1174 #define DMA_CCR_MINC_Pos (7U) macro1175 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1223 #define DMA_CCR_MINC_Pos (7U) macro1224 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1351 #define DMA_CCR_MINC_Pos (7U) macro1352 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1283 #define DMA_CCR_MINC_Pos (7U) macro1284 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1324 #define DMA_CCR_MINC_Pos (7U) macro1325 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1166 #define DMA_CCR_MINC_Pos (7U) macro1167 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1172 #define DMA_CCR_MINC_Pos (7U) macro1173 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1483 #define DMA_CCR_MINC_Pos (7U) macro1484 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1355 #define DMA_CCR_MINC_Pos (7U) macro1356 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
