1 /** 2 ****************************************************************************** 3 * @file stm32wb0x_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2024 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WB0x_HAL_DMA_H 21 #define STM32WB0x_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wb0x_hal_def.h" 29 #include "stm32wb0x_ll_dma.h" 30 31 /** @addtogroup STM32WB0x_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 } HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 } HAL_DMA_LevelCompleteTypeDef; 96 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 106 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 107 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 108 109 } HAL_DMA_CallbackIDTypeDef; 110 111 /** 112 * @brief DMA handle Structure definition 113 */ 114 typedef struct __DMA_HandleTypeDef 115 { 116 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 117 118 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 119 120 HAL_LockTypeDef Lock; /*!< DMA locking object */ 121 122 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 123 124 void *Parent; /*!< Parent object state */ 125 126 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 127 128 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 129 130 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 131 132 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 133 134 __IO uint32_t ErrorCode; /*!< DMA Error code */ 135 136 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 137 138 uint32_t ChannelIndex; /*!< DMA Channel Index */ 139 140 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 141 } DMA_HandleTypeDef; 142 /** 143 * @} 144 */ 145 146 /* Exported constants --------------------------------------------------------*/ 147 148 /** @defgroup DMA_Exported_Constants DMA Exported Constants 149 * @{ 150 */ 151 152 /** @defgroup DMA_Error_Code DMA Error Code 153 * @{ 154 */ 155 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 156 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 157 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 158 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 159 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 160 161 /** 162 * @} 163 */ 164 165 /** @defgroup DMA_request DMA request 166 * @{ 167 */ 168 169 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 170 171 #define DMA_REQUEST_ADC1_DS LL_DMAMUX_REQ_ADC1_DS /*!< DMAMUX ADC Channel 0 request */ 172 #ifdef ADC_DF_DATAOUT_DF_DATA 173 #define DMA_REQUEST_ADC1_DF LL_DMAMUX_REQ_ADC1_DF /*!< DMAMUX ADC Channel 1 request */ 174 #endif /* ADC_DF_DATAOUT_DF_DATA */ 175 #ifdef SPI1 176 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 177 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 178 #endif /* SPI1 */ 179 #ifdef SPI2 180 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 181 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 182 #endif /* SPI2 */ 183 #ifdef SPI3 184 #define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ 185 #define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ 186 #endif /* SPI3 */ 187 188 #ifdef I2C1 189 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 190 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 191 #endif /* I2C1 */ 192 #ifdef I2C2 193 #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C3 RX request */ 194 #define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C3 TX request */ 195 #endif /* I2C2 */ 196 197 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 198 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 199 200 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */ 201 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */ 202 203 #ifdef TIM2 204 #define DMAMUX_REQ_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 205 #define DMAMUX_REQ_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH3 request */ 206 #define DMAMUX_REQ_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 207 #define DMAMUX_REQ_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 208 #define DMAMUX_REQ_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 209 #endif /* TIM2 */ 210 211 #ifdef TIM16 212 #define DMAMUX_REQ_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 213 #define DMAMUX_REQ_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 214 #endif /* TIM17 */ 215 #ifdef TIM17 216 #define DMAMUX_REQ_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 217 #define DMAMUX_REQ_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 218 #endif /* TIM17 */ 219 220 221 #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ 222 /** 223 * @} 224 */ 225 226 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 227 * @{ 228 */ 229 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 230 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 231 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 232 /** 233 * @} 234 */ 235 236 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 237 * @{ 238 */ 239 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 240 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 241 /** 242 * @} 243 */ 244 245 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 246 * @{ 247 */ 248 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 249 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 255 * @{ 256 */ 257 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 258 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 259 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup DMA_Memory_data_size DMA Memory data size 265 * @{ 266 */ 267 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 268 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 269 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup DMA_mode DMA mode 275 * @{ 276 */ 277 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 278 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup DMA_Priority_level DMA Priority level 284 * @{ 285 */ 286 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 287 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 288 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 289 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 290 /** 291 * @} 292 */ 293 294 295 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 296 * @{ 297 */ 298 #define DMA_IT_TC LL_DMA_CCR_TCIE /*!< Transfer complete interrupt */ 299 #define DMA_IT_HT LL_DMA_CCR_HTIE /*!< Half Transfer interrupt */ 300 #define DMA_IT_TE LL_DMA_CCR_TEIE /*!< Transfer error interrupt */ 301 /** 302 * @} 303 */ 304 305 /** @defgroup DMA_flag_definitions DMA flag definitions 306 * @{ 307 */ 308 #define DMA_FLAG_GL1 LL_DMA_ISR_GIF1 /*!< Channel 1 global flag */ 309 #define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 310 #define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 311 #define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 312 #define DMA_FLAG_GL2 LL_DMA_ISR_GIF2 /*!< Channel 2 global flag */ 313 #define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 314 #define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 315 #define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 316 #define DMA_FLAG_GL3 LL_DMA_ISR_GIF3 /*!< Channel 3 global flag */ 317 #define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 318 #define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 319 #define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 320 #define DMA_FLAG_GL4 LL_DMA_ISR_GIF4 /*!< Channel 4 global flag */ 321 #define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 322 #define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 323 #define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 324 #define DMA_FLAG_GL5 LL_DMA_ISR_GIF5 /*!< Channel 5 global flag */ 325 #define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 326 #define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 327 #define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 328 #define DMA_FLAG_GL6 LL_DMA_ISR_GIF6 /*!< Channel 6 global flag */ 329 #define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 330 #define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 331 #define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 332 #define DMA_FLAG_GL7 LL_DMA_ISR_GIF7 /*!< Channel 7 global flag */ 333 #define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 334 #define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 335 #define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 336 #define DMA_FLAG_GL8 LL_DMA_ISR_GIF8 /*!< Channel 8 global flag */ 337 #define DMA_FLAG_TC8 LL_DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */ 338 #define DMA_FLAG_HT8 LL_DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */ 339 #define DMA_FLAG_TE8 LL_DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */ 340 /** 341 * @} 342 */ 343 344 /** 345 * @} 346 */ 347 348 /* Exported macros -----------------------------------------------------------*/ 349 /** @defgroup DMA_Exported_Macros DMA Exported Macros 350 * @{ 351 */ 352 353 /** @brief Reset DMA handle state 354 * @param __HANDLE__ DMA handle 355 * @retval None 356 */ 357 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 358 359 /** 360 * @brief Enable the specified DMA Channel. 361 * @param __HANDLE__ DMA handle 362 * @retval None 363 */ 364 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 365 366 /** 367 * @brief Disable the specified DMA Channel. 368 * @param __HANDLE__ DMA handle 369 * @retval None 370 */ 371 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 372 373 374 /* Interrupt & Flag management */ 375 376 /** 377 * @brief Returns the current DMA Channel transfer complete flag. 378 * @param __HANDLE__ DMA handle 379 * @retval The specified transfer complete flag index. 380 */ 381 382 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 383 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 384 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 385 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 386 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 387 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 388 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 389 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 390 DMA_FLAG_TC8) 391 392 /** 393 * @brief Returns the current DMA Channel half transfer complete flag. 394 * @param __HANDLE__ DMA handle 395 * @retval The specified half transfer complete flag index. 396 */ 397 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 398 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 399 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 400 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 401 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 402 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 403 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 404 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 : \ 405 DMA_FLAG_HT8) 406 407 /** 408 * @brief Returns the current DMA Channel transfer error flag. 409 * @param __HANDLE__ DMA handle 410 * @retval The specified transfer error flag index. 411 */ 412 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 413 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 418 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 419 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 420 DMA_FLAG_TE8) 421 422 /** 423 * @brief Returns the current DMA Channel Global interrupt flag. 424 * @param __HANDLE__ DMA handle 425 * @retval The specified transfer error flag index. 426 */ 427 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 428 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 : \ 435 DMA_ISR_GIF8) 436 437 /** 438 * @brief Get the DMA Channel pending flags. 439 * @param __HANDLE__ DMA handle 440 * @param __FLAG__ Get the specified flag. 441 * This parameter can be any combination of the following values: 442 * @arg DMA_FLAG_TCx: Transfer complete flag 443 * @arg DMA_FLAG_HTx: Half transfer complete flag 444 * @arg DMA_FLAG_TEx: Transfer error flag 445 * @arg DMA_FLAG_GLx: Global interrupt flag 446 * Where x can be from 1 to 8 to select the DMA Channel x flag. 447 * @retval The state of FLAG (SET or RESET). 448 */ 449 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 450 451 /** 452 * @brief Clear the DMA Channel pending flags. 453 * @param __HANDLE__ DMA handle 454 * @param __FLAG__ specifies the flag to clear. 455 * This parameter can be any combination of the following values: 456 * @arg DMA_FLAG_TCx: Transfer complete flag 457 * @arg DMA_FLAG_HTx: Half transfer complete flag 458 * @arg DMA_FLAG_TEx: Transfer error flag 459 * @arg DMA_FLAG_GLx: Global interrupt flag 460 * Where x can be from 1 to 8 to select the DMA Channel x flag. 461 * @retval None 462 */ 463 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 464 465 /** 466 * @brief Enable the specified DMA Channel interrupts. 467 * @param __HANDLE__ DMA handle 468 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 469 * This parameter can be any combination of the following values: 470 * @arg DMA_IT_TC: Transfer complete interrupt mask 471 * @arg DMA_IT_HT: Half transfer complete interrupt mask 472 * @arg DMA_IT_TE: Transfer error interrupt mask 473 * @retval None 474 */ 475 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 476 477 /** 478 * @brief Disable the specified DMA Channel interrupts. 479 * @param __HANDLE__ DMA handle 480 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 481 * This parameter can be any combination of the following values: 482 * @arg DMA_IT_TC: Transfer complete interrupt mask 483 * @arg DMA_IT_HT: Half transfer complete interrupt mask 484 * @arg DMA_IT_TE: Transfer error interrupt mask 485 * @retval None 486 */ 487 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 488 489 /** 490 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 491 * @param __HANDLE__ DMA handle 492 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 493 * This parameter can be one of the following values: 494 * @arg DMA_IT_TC: Transfer complete interrupt mask 495 * @arg DMA_IT_HT: Half transfer complete interrupt mask 496 * @arg DMA_IT_TE: Transfer error interrupt mask 497 * @retval The state of DMA_IT (SET or RESET). 498 */ 499 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 500 501 /** 502 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 503 * @param __HANDLE__ DMA handle 504 * @retval The number of remaining data units in the current DMA Channel transfer. 505 */ 506 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 507 508 /** 509 * @} 510 */ 511 512 /* Exported functions --------------------------------------------------------*/ 513 514 /** @addtogroup DMA_Exported_Functions 515 * @{ 516 */ 517 518 /** @addtogroup DMA_Exported_Functions_Group1 519 * @{ 520 */ 521 /* Initialization and de-initialization functions *****************************/ 522 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 523 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 524 /** 525 * @} 526 */ 527 528 /** @addtogroup DMA_Exported_Functions_Group2 529 * @{ 530 */ 531 /* IO operation functions *****************************************************/ 532 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 533 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 534 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 535 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 536 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 537 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 538 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 539 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 540 541 /** 542 * @} 543 */ 544 545 /** @addtogroup DMA_Exported_Functions_Group3 546 * @{ 547 */ 548 /* Peripheral State and Error functions ***************************************/ 549 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 550 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 551 /** 552 * @} 553 */ 554 555 /** 556 * @} 557 */ 558 559 /* Private macros ------------------------------------------------------------*/ 560 /** @defgroup DMA_Private_Macros DMA Private Macros 561 * @{ 562 */ 563 564 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 565 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 566 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 567 568 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 569 570 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 571 ((STATE) == DMA_PINC_DISABLE)) 572 573 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 574 ((STATE) == DMA_MINC_DISABLE)) 575 576 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) 577 578 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 579 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 580 ((SIZE) == DMA_PDATAALIGN_WORD)) 581 582 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 583 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 584 ((SIZE) == DMA_MDATAALIGN_WORD )) 585 586 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 587 ((MODE) == DMA_CIRCULAR)) 588 589 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 590 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 591 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 592 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 593 594 /** 595 * @} 596 */ 597 598 /* Private functions ---------------------------------------------------------*/ 599 600 /** 601 * @} 602 */ 603 604 /** 605 * @} 606 */ 607 608 #ifdef __cplusplus 609 } 610 #endif 611 612 #endif /* STM32WB0x_HAL_DMA_H */ 613
