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Searched refs:DMA2_BASE (Results 1 – 25 of 173) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h627 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
628 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
629 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
630 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
631 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
632 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
633 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
634 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
635 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
695 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32f410rx.h627 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
628 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
629 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
630 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
631 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
632 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
633 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
634 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
635 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
695 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32f410tx.h620 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
621 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
622 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
623 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
624 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
625 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
626 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
627 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
628 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
685 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32f401xc.h709 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
710 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
711 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
712 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
713 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
714 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
715 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
716 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
717 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
797 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32f401xe.h709 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
710 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
711 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
712 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
713 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
714 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
715 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
716 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
717 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
797 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32f411xe.h711 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) macro
712 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
713 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
714 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
715 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
716 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
717 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
718 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
719 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
800 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h831 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) macro
843 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
844 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
845 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
846 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
847 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
848 #define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL)
849 #define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL)
946 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32wle5xx.h831 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) macro
843 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
844 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
845 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
846 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
847 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
848 #define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL)
849 #define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL)
946 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32wl5mxx.h995 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) macro
1007 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
1008 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
1009 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
1010 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
1011 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
1012 #define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL)
1013 #define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL)
1116 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h906 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) macro
923 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
924 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
925 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
926 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
927 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
928 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
929 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
930 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
997 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l412xx.h873 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) macro
890 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
891 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
892 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
893 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
894 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
895 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
896 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
897 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
963 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xc.h905 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) macro
922 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
923 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
924 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
925 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
926 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
927 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
928 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
929 #define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
1027 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h661 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
662 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
663 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
664 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
665 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
666 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
738 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l151xc.h692 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
693 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
694 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
695 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
696 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
697 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
774 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l151xca.h694 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
695 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
696 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
697 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
698 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
699 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
778 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l151xdx.h709 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
710 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
711 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
712 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
713 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
714 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
795 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l151xe.h709 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
710 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
711 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
712 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
713 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
714 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
795 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l152xc.h708 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
709 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
710 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
711 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
712 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
713 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
791 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l152xca.h710 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
711 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
712 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
713 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
714 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
715 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
795 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l152xdx.h725 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
726 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
727 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
728 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
729 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
730 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
812 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l152xe.h725 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
726 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
727 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
728 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
729 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
730 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
812 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l162xc.h729 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
730 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
731 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
732 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
733 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
734 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
813 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l162xca.h731 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
732 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
733 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
734 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
735 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
736 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
817 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l162xdx.h746 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
747 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
748 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
749 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
750 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
751 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
834 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Dstm32l162xe.h746 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
747 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
748 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
749 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
750 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
751 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
834 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)

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