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Searched refs:DMA1_Stream5 (Results 1 – 25 of 100) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_dma.h414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Dstm32f7xx_ll_dma.h435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
458 …== ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_dma.h430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Dstm32f2xx_ll_dma.h422 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
445 …== ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_dma.h440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Dstm32f4xx_ll_dma.h432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
455 …== ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_dma.h725 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
794 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
829 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
863 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
898 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
931 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
955 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Dstm32h7xx_ll_dma.h427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
450 …== ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_dma.h602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
625 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
648 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
671 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
695 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Dstm32mp1xx_ll_dma.h412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
435 …== ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h692 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
7070 ((INSTANCE) == DMA1_Stream5) || \
Dstm32f410rx.h692 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
7074 ((INSTANCE) == DMA1_Stream5) || \
Dstm32f410tx.h682 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
7030 ((INSTANCE) == DMA1_Stream5) || \
Dstm32f401xc.h794 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
8260 ((INSTANCE) == DMA1_Stream5) || \
Dstm32f401xe.h794 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
8260 ((INSTANCE) == DMA1_Stream5) || \
Dstm32f411xe.h797 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
8291 ((INSTANCE) == DMA1_Stream5) || \
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h2497 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
21737 ((INSTANCE) == DMA1_Stream5) || \
21789 ((INSTANCE) == DMA1_Stream5) || \
21825 ((INSTANCE) == DMA1_Stream5) || \
21843 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h7b0xx.h2620 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
22217 ((INSTANCE) == DMA1_Stream5) || \
22269 ((INSTANCE) == DMA1_Stream5) || \
22305 ((INSTANCE) == DMA1_Stream5) || \
22323 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h7b0xxq.h2621 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
22229 ((INSTANCE) == DMA1_Stream5) || \
22281 ((INSTANCE) == DMA1_Stream5) || \
22317 ((INSTANCE) == DMA1_Stream5) || \
22335 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h7a3xxq.h2498 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
21749 ((INSTANCE) == DMA1_Stream5) || \
21801 ((INSTANCE) == DMA1_Stream5) || \
21837 ((INSTANCE) == DMA1_Stream5) || \
21855 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h7b3xx.h2620 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
22224 ((INSTANCE) == DMA1_Stream5) || \
22276 ((INSTANCE) == DMA1_Stream5) || \
22312 ((INSTANCE) == DMA1_Stream5) || \
22330 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h7b3xxq.h2621 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
22236 ((INSTANCE) == DMA1_Stream5) || \
22288 ((INSTANCE) == DMA1_Stream5) || \
22324 ((INSTANCE) == DMA1_Stream5) || \
22342 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h730xxq.h2728 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
23963 ((INSTANCE) == DMA1_Stream5) || \
23999 ((INSTANCE) == DMA1_Stream5) || \
24035 ((INSTANCE) == DMA1_Stream5) || \
24053 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h733xx.h2727 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
23951 ((INSTANCE) == DMA1_Stream5) || \
23987 ((INSTANCE) == DMA1_Stream5) || \
24023 ((INSTANCE) == DMA1_Stream5) || \
24041 ((INSTANCE) == DMA1_Stream5) || \
Dstm32h725xx.h2605 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) macro
23476 ((INSTANCE) == DMA1_Stream5) || \
23512 ((INSTANCE) == DMA1_Stream5) || \
23548 ((INSTANCE) == DMA1_Stream5) || \
23566 ((INSTANCE) == DMA1_Stream5) || \

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