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Searched refs:DMA1_Stream0_BASE (Results 1 – 25 of 92) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h619 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
687 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f410rx.h619 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
687 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f410tx.h612 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
677 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f401xc.h701 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
789 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f401xe.h701 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
789 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f411xe.h703 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
792 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f405xx.h898 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1013 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f412cx.h875 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
981 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f415xx.h966 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1084 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f423xx.h1062 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1202 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f407xx.h994 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1115 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f412zx.h924 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1038 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f412rx.h921 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1032 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f412vx.h922 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1034 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f413xx.h1028 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1167 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h950 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1066 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f205xx.h904 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1018 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f207xx.h1000 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1120 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h1030 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1148 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Dstm32f722xx.h1016 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) macro
1133 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

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