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Searched refs:DMA1_Ch4_5_DMAMUX1_OVR_IRQn (Results 1 – 3 of 3) sorted by relevance

/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h87 …DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interru… enumerator
Dstm32g031xx.h88 …DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interru… enumerator
Dstm32g041xx.h88 …DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interru… enumerator