Searched refs:DMA1_CSELR_CH4_TIM2_CH4_Msk (Results 1 – 3 of 3) sorted by relevance
1320 #define DMA1_CSELR_CH4_TIM2_CH4_Msk (0x5UL << DMA1_CSELR_CH4_TIM2_CH4_Pos) /*!< 0x00005000 */ macro1321 #define DMA1_CSELR_CH4_TIM2_CH4 DMA1_CSELR_CH4_TIM2_CH4_Msk /*!< Remap TIM2 chan…
5807 #define DMA1_CSELR_CH4_TIM2_CH4_Msk (0x5UL << DMA1_CSELR_CH4_TIM2_CH4_Pos) /*!< 0x00005000 */ macro5808 #define DMA1_CSELR_CH4_TIM2_CH4 DMA1_CSELR_CH4_TIM2_CH4_Msk /*!< Remap TIM2 chan…