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Searched refs:DIVIDER_Q_UPDATE (Results 1 – 4 of 4) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c45 #define DIVIDER_Q_UPDATE 1U macro
664 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
669 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
716 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
721 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
772 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
815 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
969 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
974 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
1020 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
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/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_rcc_ex.c48 #define DIVIDER_Q_UPDATE 1U macro
558 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
595 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
626 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
785 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
3034 else if(Divider == DIVIDER_Q_UPDATE) in RCCEx_PLLSAI1_Config()
3240 else if(Divider == DIVIDER_Q_UPDATE) in RCCEx_PLLSAI2_Config()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_rcc_ex.c48 #define DIVIDER_Q_UPDATE 1U macro
540 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
565 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
606 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); in HAL_RCCEx_PeriphCLKConfig()
2596 else if (Divider == DIVIDER_Q_UPDATE) in RCCEx_PLLSAI1_Config()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_rcc_ex.c46 #define DIVIDER_Q_UPDATE 1U macro