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Searched refs:DDRPHYC_ZQ0SR1_ZPU_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9442 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9443 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9445 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9446 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_cm4.h9605 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9606 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9608 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9609 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151axx_ca7.h9442 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9443 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9445 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9446 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151axx_cm4.h9408 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9409 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9411 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9412 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151dxx_cm4.h9408 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9409 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9411 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9412 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_ca7.h9639 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9640 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9642 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9643 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_cm4.h9605 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9606 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9608 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9609 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_ca7.h9639 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
9640 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
9642 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
9643 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153axx_ca7.h10993 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
10994 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
10996 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
10997 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153axx_cm4.h10959 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
10960 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
10962 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
10963 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_ca7.h11190 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11191 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11193 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11194 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_cm4.h11156 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11157 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11159 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11160 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_ca7.h10993 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
10994 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
10996 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
10997 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_cm4.h10959 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
10960 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
10962 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
10963 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_ca7.h11190 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11191 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11193 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11194 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_cm4.h11156 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11157 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11159 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11160 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157axx_ca7.h11108 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11109 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11111 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11112 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157axx_cm4.h11074 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11075 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11077 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11078 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_ca7.h11305 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11306 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11308 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11309 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_cm4.h11271 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11272 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11274 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11275 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_ca7.h11108 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11109 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11111 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11112 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_cm4.h11074 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11075 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11077 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11078 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_ca7.h11305 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11306 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11308 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11309 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_cm4.h11271 #define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) macro
11272 #define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
11274 #define DDRPHYC_ZQ0SR1_ZPU_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
11275 #define DDRPHYC_ZQ0SR1_ZPU_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */