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Searched refs:DDRPHYC_ZQ0SR1_ZPD_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9437 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9438 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9440 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9441 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151fxx_cm4.h9600 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9601 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9603 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9604 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151axx_ca7.h9437 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9438 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9440 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9441 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151axx_cm4.h9403 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9404 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9406 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9407 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151dxx_cm4.h9403 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9404 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9406 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9407 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151cxx_ca7.h9634 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9635 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9637 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9638 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151cxx_cm4.h9600 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9601 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9603 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9604 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp151fxx_ca7.h9634 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
9635 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
9637 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
9638 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153axx_ca7.h10988 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
10989 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
10991 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
10992 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153axx_cm4.h10954 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
10955 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
10957 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
10958 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153cxx_ca7.h11185 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11186 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11188 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11189 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153cxx_cm4.h11151 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11152 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11154 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11155 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153dxx_ca7.h10988 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
10989 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
10991 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
10992 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153dxx_cm4.h10954 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
10955 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
10957 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
10958 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153fxx_ca7.h11185 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11186 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11188 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11189 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp153fxx_cm4.h11151 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11152 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11154 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11155 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157axx_ca7.h11103 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11104 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11106 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11107 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157axx_cm4.h11069 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11070 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11072 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11073 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157cxx_ca7.h11300 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11301 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11303 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11304 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157cxx_cm4.h11266 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11267 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11269 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11270 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157dxx_ca7.h11103 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11104 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11106 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11107 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157dxx_cm4.h11069 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11070 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11072 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11073 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157fxx_ca7.h11300 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11301 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11303 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11304 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
Dstm32mp157fxx_cm4.h11266 #define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) macro
11267 #define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
11269 #define DDRPHYC_ZQ0SR1_ZPD_0 (0x1UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
11270 #define DDRPHYC_ZQ0SR1_ZPD_1 (0x2UL << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */