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Searched refs:DDRPHYC_ZQ0SR0_ZERR_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9429 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9430 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151fxx_cm4.h9592 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9593 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151axx_ca7.h9429 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9430 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151axx_cm4.h9395 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9396 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151dxx_cm4.h9395 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9396 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151cxx_ca7.h9626 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9627 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151cxx_cm4.h9592 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9593 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp151fxx_ca7.h9626 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
9627 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153axx_ca7.h10980 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
10981 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153axx_cm4.h10946 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
10947 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153cxx_ca7.h11177 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11178 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153cxx_cm4.h11143 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11144 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153dxx_ca7.h10980 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
10981 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153dxx_cm4.h10946 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
10947 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153fxx_ca7.h11177 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11178 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp153fxx_cm4.h11143 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11144 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157axx_ca7.h11095 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11096 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157axx_cm4.h11061 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11062 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157cxx_ca7.h11292 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11293 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157cxx_cm4.h11258 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11259 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157dxx_ca7.h11095 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11096 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157dxx_cm4.h11061 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11062 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157fxx_ca7.h11292 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11293 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
Dstm32mp157fxx_cm4.h11258 #define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) macro
11259 #define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1UL << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */