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Searched refs:DDRPHYC_ZQ0CR1_ZPROG_2 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h9398 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151fxx_cm4.h9561 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151axx_ca7.h9398 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151axx_cm4.h9364 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151dxx_cm4.h9364 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151cxx_ca7.h9595 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151cxx_cm4.h9561 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp151fxx_ca7.h9595 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153axx_ca7.h10949 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153axx_cm4.h10915 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153cxx_ca7.h11146 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153cxx_cm4.h11112 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153dxx_ca7.h10949 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153dxx_cm4.h10915 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153fxx_ca7.h11146 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp153fxx_cm4.h11112 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157axx_ca7.h11064 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157axx_cm4.h11030 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157cxx_ca7.h11261 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157cxx_cm4.h11227 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157dxx_ca7.h11064 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157dxx_cm4.h11030 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157fxx_ca7.h11261 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro
Dstm32mp157fxx_cm4.h11227 #define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4UL << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ macro