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Searched refs:DDRPHYC_PGCR_IOLB_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8368 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8369 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_cm4.h8531 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8532 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151axx_ca7.h8368 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8369 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151axx_cm4.h8334 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8335 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151dxx_cm4.h8334 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8335 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_ca7.h8565 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8566 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151cxx_cm4.h8531 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8532 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp151fxx_ca7.h8565 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
8566 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153axx_ca7.h9919 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
9920 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153axx_cm4.h9885 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
9886 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_ca7.h10116 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10117 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153cxx_cm4.h10082 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10083 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_ca7.h9919 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
9920 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153dxx_cm4.h9885 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
9886 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_ca7.h10116 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10117 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp153fxx_cm4.h10082 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10083 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157axx_ca7.h10034 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10035 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157axx_cm4.h10000 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10001 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_ca7.h10231 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10232 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157cxx_cm4.h10197 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10198 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_ca7.h10034 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10035 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157dxx_cm4.h10000 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10001 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_ca7.h10231 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10232 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
Dstm32mp157fxx_cm4.h10197 #define DDRPHYC_PGCR_IOLB_Pos (15U) macro
10198 #define DDRPHYC_PGCR_IOLB_Msk (0x1UL << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */